Browsing by Author "Wu, Ming-Ju"

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A Storage Device Emulator for System Performance Evaluation
(2015-12-01)
Wu, Ming-Ju
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Tsai, Chun-Jen
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資訊工程學系
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Department of Computer Science
The performance and characteristics of the storage devices used in embedded systems can have a great influence on the overall end user experience. When building embedded systems or designing new storage device components, it is important for the designers to be able to evaluate how storage devices of different characteristics will affect the overall system performance. Storage device emulation enables a system\'s performance to be evaluated with simulated storage devices that are not yet available. In storage device emulation, the emulated storage device appears to the operating system (OS) as a real storage device and its service timings are determined by a disk model, which simulates the behavior of the target storage device. In the conventional storage device emulators, because the OS is running continuously in the real-time domain, the amount of time that the emulators can spend on processing each I/O request is limited by the service time of each corresponding I/O request. This timing constraint can make emulating high-speed storage devices a challenge for the conventional storage device emulators. In this article, we propose an OS state pausing approach to storage device emulation that can overcome the timing constraints faced by the conventional storage device emulators. By pausing the state of the OS while the storage device emulator is busy, the proposed emulator can spend as much time as it needs for processing each I/O request without affecting the performance of the emulated storage device as perceived by the OS. This allows the proposed storage device emulator to emulate storage devices that would otherwise be challenging or even impossible for the conventional storage device emulators. In addition, the main task of storage device emulation is offloaded to an external computer to minimize the impact of the emulation workload on the target machine. The proposed storage device emulator is implemented with the Linux OS1 on an embedded system development board. Experimental results show that the full-system performance benchmarks measured with the proposed storage device emulator are within 2% differences compared to the results of the reference system.
Bandgap Engineering Enhances the Performance of Mixed-Cation Perovskite Materials for Indoor Photovoltaic Applications
(2019-10-01)
Wu, Ming-Ju
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Kuo, Chien-Chen
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Jhuang, Lu-Syuan
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Chen, Po-Han
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Lai, Yi-Fong
Indoor photovoltaics (IPVs) are attracting renewed interest because they can provide sustainable energy through the recycling of photon energy from household lighting facilities. Herein, the Shockley-Queisser model is used to calculate the upper limits of the power conversion efficiencies (PCEs) of perovskite solar cells (PeSCs) for two types of artificial light sources: fluorescent tubes (FTs) and white light-emitting diodes (WLEDs). An unusual zone is found in which the dependence of the PCEs on the bandgap (E-g) under illumination from the indoor lighting sources follows trends different from that under solar irradiation. In other words, IPVs exhibiting high performance under solar irradiation may not perform well under indoor lighting conditions. Furthermore, the ideal bandgap energy for harvesting photonic power from these indoor lighting sources is approximate to 1.9 eV-a value higher than that of common perovskite materials (e.g., for CH3NH3PbI3). Accordingly, Br- ions are added into the perovskite films to increase their values of E-g. A resulting PeSC featuring a wider bandgap exhibits PCEs of 25.94% and 25.12% under illumination from an FT and a WLED, respectively. Additionally, large-area (4 cm(2)) devices are prepared for which the PCE reaches approximate to 18% under indoor lighting conditions.
Dynamic Pipeline-Partitioned Video Decoding on Symmetric Stream Multiprocessors
(2015)
Wu, Ming-Ju
;
Chen, Yan-Ting
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Tsai, Chun-Jen
;
資訊工程學系
;
Department of Computer Science
In this paper, we have implemented a dynamic pipeline-partitioning video decoder for the symmetric stream multiprocessor (SSMP) architecture. The SSMP architecture extends the traditional symmetric multiprocessor (SMP) architecture with dedicated per-core scratchpad memories and inter-processor communication (IPC) controllers for efficient data passing between the processor cores. The SSMP architecture allows the processor cores to cooperate efficiently in a fine-grained software pipeline fashion. A traditional software pipelined video decoder has fixed pipeline-stage partitions. The AVC/H.264 video decoder investigated in this paper dynamically assigns different stages of the video macroblock (MB) decoding tasks to different processor cores in order to maintain load balance among the processor cores. The pipeline partitioning policy is based on the queue levels of the inter-stage buffers. Experimental results show that, on average, the proposed dynamic pipeline-partitioning video decoder is 34% faster compared to a wavefront-based parallel video decoder.
Hardware-assisted Syntax Decoding Model for Software AVC/H.264 Decoders
(2009)
Wu, Ming-Ju
;
Chen, Yi-Tseng
;
Tsai, Chun-Jen
;
資訊工程學系
;
Department of Computer Science
In this paper, we have proposed an efficient hardware-assisted syntax decoding model for software-based video decoder. The proposed syntax decoding model is a generic model for different video codec standards. The syntax decoding process is divided into codec-dependent high-level syntax parser and generic entropy decoding engines. Currently, the design is implemented specifically for the support of AVC/H.264 standard (for both CAVLC and CABAC acceleration). Nevertheless, the design of the proposed syntax decoding model has the potential of becoming the design of a flexible bitstream parser, which is the most challenging problem in the MPEG Reconfigurable Video Coding (RVC) Framework A Virtex-5 FPGA development board is used to implement and verify the full hardware-software system (including the hardware entropy engines and the software syntax parser and macroblock data reconstruction modules extracted from JM12.2).