Browsing by Author "Wu, P. C."

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The Observation of BTI-induced RTN Traps in Inversion and Accumulation Modes on HfO2 High-k Metal Gate 28nm CMOS Devices
(2014-01-01)
Wu, P. C.
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Hsieh, E. R.
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Lu, P. Y.
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Chung, Steve S.
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Chang, K. Y.
A comprehensive analysis on the BTI induced RTN traps in high-k(HK) CMOS devices have been investigated in inversion (inv.) and accumulation (acc.) modes. The combination of two modes for RTN measurement provides a wide range of energy window in high-k gate dielectric, in which a simple extraction method of RTN analysis has been adopted to analyze the gate dielectric dual-layer of advanced HK devices. The results show that inversion mode measurement can only identify the RTN traps in the channel region, which is related to the V-th degradation. While, accumulation mode may detect the traps inside the gate-drain overlap region which provides better understanding of GIDL current. This basic understanding is of critical important to the quality development of HK gate dielectrics in advanced CMOS technologies.
The Understanding of the Bulk Trigate MOSFET's Reliability Through the Manipulation of RTN Traps
(2013)
Hsieh, E. R.
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Wu, P. C.
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Chung, Steve S.
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Tsai, C. H.
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Huang, R. M.
The manipulation of RTN-trap profiling bas been experimentally demonstrated on both planar and trigate MOSFETs. It was achieved by a simple experimental method to take the 2D profiling of the RTN-trap in both oxide depth (vertical) and channel (lateral) directions in the gate oxide. Then, by arranging various 2D fields for the device stress condition, the positions of RTN traps can be precisely controlled. This is the first being reported that the positions of RTN-traps can be manipulated, showing significant advances for the understanding of the trap generation and the impact on the device reliability. Results have demonstrated why trigate exhibits much worse reliability than the planar ones.