Browsing by Author "Wu, Pei-Si"

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A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression
(2015-03-01)
Su, Ming-Chiuan
;
Chen, Wei-Zen
;
Wu, Pei-Si
;
Chen, Yu-Hsiang
;
Lee, Chao-Cheng
A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UI(pp) jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 ps(rms). The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm(2) only. It dissipates 12.4 mW from 1 V supply.
A 10Gbps, 1.24pJ/bit, Burst-Mode Clock and Data Recovery with Jitter Suppression
(2013-01-01)
Su, Ming-Chiuan
;
Chen, Wei-Zen
;
Wu, Pei-Si
;
Chen, Yu-Hsian
;
Lee, Chao-Cheng
A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1: 5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UI(pp) input data jitter, the recovered clock jitter at 2GHz is 2.94ps(rms). The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200x150 mu m(2).