Browsing by Author "Wu, Shang-Lin"

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0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process
(2018-01-01)
Chan, Yun-Sheng
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Huang, Po-Tsang
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Wu, Shang-Lin
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Lung, Sheng-Chi
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Wang, Wei-Chang
This paper presents a near-threshold configurable ternary content addressable memory (TCAM) design for energy-constrained neural network or software-defined network (SDN) applications. A TCAM architecture based on foundry-based 6T SRAM mini-array improves area efficiency and minimizes disturbs to enable operation down to 0.4V, and provides configurable lookup tables for users. To minimize dynamic power consumption, hierarchical precharge structure (HPRE) and don't-care based ripple search-line scheme are utilized for decreasing both the switching activities and wire capacitance. Moreover, power-gating technique, self-timed control and V-trip-tracking write-assist are used to reduce standby power, speed-up propagation delays of global signals and improve write-ability at low voltage, respectively. A reconfigurable TCAM is implemented using UMC 28nm high-k metal gate (HKMG) CMOS process. The design achieves operating frequency of 240MHz (20MHz) with energy consumption of 1.146 (0.621) fJ/bit/search at 0.9V (0.4V).
2.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural-Sensing Applications
(2014-01-01)
Huang, Po-Tsang
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Chou, Lei-Chun
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Huang, Teng-Chieh
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Wu, Shang-Lin
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Wang, Tang-Shuan
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications
(2014-12-01)
Huang, Po-Tsang
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Wu, Shang-Lin
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Huang, Yu-Chieh
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Chou, Lei-Chun
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Huang, Teng-Chieh
Heterogeneously integrated and miniaturized neural sensing microsystems are crucial for brain function investigation. In this paper, a 2.5D heterogeneously integrated bio-sensing microsystem with mu-probes and embedded through-silicon-via (TSVs) is presented for high-density neural sensing applications. This microsystem is composed of mu-probes with embedded TSVs, 4 dies and a silicon interposer. For capturing 16-channel neural signals, a 24 x 24 mu-probe array with embedded TSVs is fabricated on a 5 x 5 mm2 chip and bonded on the back side of the interposer. Thus, each channel contains 6 x 6 mu-probes with embedded TSVs. Additionally, the 4 dies are bonded on the front side of the interposer and designed for biopotential acquisition, feature extraction and classification via low-power analog front-end (AFE) circuits, area-power-efficient analog-to-digital converters (ADCs), configurable discrete wavelet transforms (DWTs), filters, and a MCU. An on-interposer bus (mu-SPI) is designed for transferring data on the interposer. Finally, the successful in-vivo test demonstrated the proposed 2.5D heterogeneously integrated bio-sensing microsystem. The overall power of this microsystem is only 676.3 mu W for 16-channel neural sensing.
28nm Near/Sub-Threshold Dual-Port FIFO Memory for Shared Queues in Multi-Sensor Applications
(2018-01-01)
Wu, Yi-Chun
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Huang, Po-Tsang
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Wu, Shang-Lin
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Lung, Sheng-Chi
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Wang, Wei-Chang
For an energy-limited multi-sensing platform, ultra-low-power queueing design is one of the critical challenge to store low-speed sensing data with various sampling frequencies. In this paper, a near/sub-threshold dual-port first-in-first-out (FIFO) memory is proposed for shared queues in a unified queuing architecture. This ultra-lowpower FIFO memory is designed and implemented using bitinterleaved 12T near-/sub-threshold dual-port SRAM bit-cells, write/read-assist circuitries, and adaptive timing tracking circuits. The 12T bit-cell eliminates both read and write half-select disturbance. Additionally, an adaptive timing tracing circuitry and negative bit-line circuits are employed to against PVT variation and to enhance write ability, respectively. Furthermore, the self-timed pointers and short ripple bit-lines are designed to avoid global long metal lines with large loading. A 256x16 dual-port FIFO memory is implemented in UMC 28nm HKMG CMOS technology. This FIFO memory can be operated at 0.4V with 10MHz for read operations. Moreover, up to 60% power reduction can be achieved based on the proposed design techniques.
28nm Ultra-Low Power Near-/Sub- threshold First-In-First-Out (FIFO) Memory for Multi-Bio-Signal Sensing Platforms
(2016)
Hsu, Wei-Shen
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Huang, Po-Tsang
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Wu, Shang-Lin
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Chuang, Ching-Te
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Hwang, Wei
In this paper, an ultra-low-power near-/sub-threshold first-in-firstout (FIFO) memory is proposed for energy-constrained bio-signal sensing applications. This FIFO memory is designed and implemented using folded bit-interleaved 10T near-/sub-threshold SRAM bit-cells, self-timed pointers and bank-level power control circuits. The 10T SRAM cell is proposed for the bit-interleaving structure with 2.4X write static noise margin (SNM) improvement. The folded bit-interleaving structure reduces the bit-line capacitance and avoids long routing wires for the circular self-timed pointers. Additionally, the event-driven self-timed pointers are designed to reduce the power consumption of clock buffers. For further decreasing the overall power dissipation, bank-level column-based power control circuitry is proposed to switch the voltages for different banks to achieve 60.5% power saving. A 512x16 FIFO memory is implemented in UMC 28nm HKMG CMOS technology. Compared with the prior arts, 47X power reduction and 2.7X area efficiency can be achieved by the proposed design techniques.
A 0.35 V, 375 kHz, 5.43 mu W, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line
(2016-05)
Wu, Shang-Lin
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Lu, Chien-Yu
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Tu, Ming-Hsien
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Huang, Huan-Shun
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Lee, Kuen-Di
This paper presents a disturb-free 10T subthreshold SRAM cell with fully-symmetrical structure and tristate pre-charge free bit-line (BL). The disturb-free feature facilitates bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The fully-symmetrical cell structure provides balanced margin and performance in advanced strained-silicon and/or FinFET technologies where PMOS strength approaches that of NMOS. The tri-state BL is left floating in standby state to minimize switching activity for energy efficiency. The scheme eliminates the need of BL keeper, provides balanced two-transistor stack read for better read performance, and eases the design and migration. The proposed 10T SRAM cell is demonstrated by 128 kb SRAM macro implemented in 40 nm low-power (40LP) CMOS technology. Measured read and write functionality is demonstrated with V-DD down to 0.35 V (similar to 100 mV lower than the threshold voltage). Data is held down to 0.325 V with 2.53 mu W standby power. The measured maximum operation frequency is 375 kHz with total power consumption 5.43 mu W at 0.35 V. (C) 2016 Elsevier Ltd. All rights reserved.
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
(2017-07-01)
Wu, Shang-Lin
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Li, Kuang-Yu
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Huang, Po-Tsang
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Hwang, Wei
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Tu, Ming-Hsien
This paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-b length to improve variation tolerance and performance, and to reduce disturb while maintaining manufacturability. The design employs threshold power gating to facilitate lower NAP (Sleep) mode voltage/power and faster wake-up for the cell array, and low-swing global read bit-line (GRBL) with integrated low-swing voltage precharger to improve read performance and reduce the dynamic read power. A cell Vtrip-tracking write-assist (VTWA) lowers the selected sub-array supply to cell inverter trip voltage to enhance write-ability while providing PVT tracking capability to ensure adequate data retention margin for unselected cells in the selected sub-array. The 256-kb test chip is implemented in UMC 28-nm high-kappa metal-gate (H kappa MG) CMOS technology with macro area of 1058.22 x 374.76 mu m(2). Error-free full functionality is achieved from 0.9 down to 0.5 V (limited by read VMIN) without redundancy. The low-swing GRBL reduces dynamic power by 6.5% (8.0%) at 0.9 V (0.6 V). The VTWA improves the write VMIN by 75 mV (from 0.525 to 0.45 V). The measured maximum operation frequency is 735 MHz (20 MHz) at 0.9 V (0.5 V), TT corner, 25(omicron).
A 64-CHANNEL WIRELESS NEURAL SENSING MICROSYSTEM WITH TSV-EMBEDDED MICRO-PROBE ARRAY FOR NEURAL SIGNAL ACQUISITION
(2017-01-01)
Huang, Yu-Chieh
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Huang, Po-Tsang
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Hu, Yu-Chen
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Wu, Shang-Lin
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You, Yan-Huei
To enhance the signal integrity of high-density neural-sensing signals, this work presents an implantable high spatial resolution mu-probe array with through-silicon via (TSV) 2.5D integration technology that realizes a miniaturized implantable device on flexible printed circuit (FPC) interposer. The proposed microsystem was composed of two 32-channel neural sensing chips and one radio frequency chip for neural signal processing. The mu-probe array can achieve better signal-to-noise ratio with neural-signal acquisition and processing circuit composed of a pseudo-resistor-based analog front-end amplifier. Moreover, a receiving antenna is also implemented on the backside of FPC for wireless data and power transmission. The feasibility of the proposed mu-probe array, Tx and Rx antenna, 32-channel neural sensing circuits in the 64-channel wireless microsystem have been successfully demonstrated for future integration and animal experiments.
A double-sided, single-chip integration scheme using through-silicon-via for neural sensing applications
(2015-02-01)
Chang, Chih-Wei
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Chou, Lei-Chun
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Huang, Po-Tsang
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Wu, Shang-Lin
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Lee, Shih-Wei
We present a new double-sided, single-chip monolithic integration scheme to integrate the CMOS circuits and MEMS structures by using through-silicon-via (TSV). Neural sensing applications were chosen as the implementation example. The proposed heterogeneous device integrates standard 0.18 mu m CMOS technology, TSV and neural probe array into a compact single chip device. The neural probe array on the back-side of the chip is connected to the CMOS circuits on the front-side of the chip by using low-parasitic TSVs through the chip. Successful fabrication results and detailed characterization demonstrate the feasibility and performance of the neural probe array, TSV and readout circuitry. The fabricated device is 5x5 mm(2) in area, with 16 channels of 150 mu m-in-length neural probe array on the back-side, 200 mu m-deep TSV through the chip and CMOS circuits on the front-side. Each channel consists of a 5x6 probe array, 3x14 TSV array and a differential-difference amplifier (DDA) based analog front-end circuitry with 1.8 V supply, 21.88 mu W power consumption, 108 dB CMRR and 2.56 mu Vrms input referred noise. In-vivo long term implantation demonstrated the feasibility of presented integration scheme after 7 and 58 days of implantation. We expect the conceptual realization can be extended for higher density recording array by using the proposed method.
A global optimized neuro-fuzzy system using artificial bee colony evolutionary algorithm
(2015-01-01)
Liu, Yu-Ting
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Lin, Yang-Yin
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Hsieh, Tsung-Yu
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Wu, Shang-Lin
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Lin, Chin-Teng
This paper proposes a novel Takagi-Sugeno-Kang-type (TSK-type) neuro-fuzzy system (NFS), which utilizes the artificial bee colony (ABC) evolutionary algorithm for parameter optimization. The ABC evolutionary algorithm was developed based on imitating foraging behavior of natural bees for numerical optimization problems, and it has been proved to outperform other metaheuristic approaches on different constrain optimization problems in previous studies. The proposed NFS in this paper adopts an adaptive clustering method to generate fuzzy rules for determining the system architecture, and the TSK-type reasoning is employed for the consequent part of each rule. Subsequently, all free parameters in the NFS designed, including the premise and the consequent parameters, will be optimized by ABC algorithm. This study compares the performance of ABC algorithm with that of Genetic Algorithm (GA), Particle Swarm Optimization (PSO) and Differential Evolution (DE). The simulation results show that the performance of ABC algorithm is superior to that of the mentioned algorithms for solving dynamic system problems.
A Hybrid of Cuckoo Search and Simplex Method for Fuzzy Neural Network Training
(2015)
Chang, Jyh-Yeong
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Liao, Shih-Hui
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Wu, Shang-Lin
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Lin, Chin-Teng
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電控工程研究所
In this paper, a new hybrid algorithm mixing the simplex method of Nelder and Mead (NM) and the cuckoo search (CS), abbreviated as NM-CS, is proposed for the training of the Fuzzy Neural Networks (FNNs). In standard CS, cuckoo birds engage the obligate brood parasitism by laying their own eggs to other host birds. If a host bird discovers the alien eggs, they will either throw these eggs away or abandon its nest and build a new nest elsewhere. In the proposed hybrid algorithm, instead of using the probability to discover an alien egg for the CS, we use the concept of a simplex which is used in the NM algorithm to abandon and generate the new nests. Our proposed method puts more emphasis on exploration of the search space and enhances the ability to avoid local optimum. Some simulation problems will be provided to compare the performances of the proposed method and other methods in training an FNN. In these simulations, it is observed that the proposed method outperforms other methods.
A Learning Scheme to Fuzzy C-Means based on a Compromise in Updating Membership Degrees
(2014-01-01)
Wu, Shang-Lin
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Lin, Yang-Yin
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Liu, Yu-Ting
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Chen, Chih-Yu
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Lin, Chin-Teng
Fuzzy C-Means (FCM) clustering is the most well-known clustering method according to fuzzy partition for pattern classification. However, there are some disadvantages of using that clustering method, such as computational complexity and execution time. Therefore, to solve these drawbacks of FCM, the two-phase FCM procedure has been proposed in this study. Compared with the conventional FCM, the usage of a compromised learning scheme makes more adaptive and effective. By performing the proposed approach, the unknown data could be rapidly clustered according to the previous information. A synthetic data set with two dimensional variables is generated to estimate the performance of the proposed method, and to further demonstrate that our method not only reduces computational complexity but economizes execution time compared with the conventional FCM in each example.
A Motor Imagery Based Brain-Computer Interface System via Swarm-Optimized Fuzzy Integral and Its Application
(2016)
Wu, Shang-Lin
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Liu, Yu-Ting
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Chou, Kuang-Pen
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Lin, Yang-Yin
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Lu, Jie
A brain-computer interface (BCI) system provides a convenient means of communication between the human brain and a computer, which is applied not only to healthy people but also for people that suffer from motor neuron diseases (MNDs). Motor imagery (MI) is one well-known basis for designing Electroencephalography (EEG)-based real-life BCI systems. However, EEG signals are often contaminated with severe noise and various uncertainties, imprecise and incomplete information streams. Therefore, this study proposes spectrum ensemble based on swam-optimized fuzzy integral for integrating decisions from sub-band classifiers that are established by a sub-band common spatial pattern (SBCSP) method. Firstly, the SBCSP effectively extracts features from EEG signals, and thereby the multiple linear discriminant analysis (MLDA) is employed during a MI classification task. Subsequently, particle swarm optimization (PSO) is used to regulate the subject-specific parameters for assigning optimal confidence levels for classifiers used in the fuzzy integral during the fuzzy fusion stage of the proposed system. Moreover, BCI systems usually tend to have complex architectures, be bulky in size, and require time-consuming processing. To overcome this drawback, a wireless and wearable EEG measurement system is investigated in this study. Finally, in our experimental result, the proposed system is found to produce significant improvement in terms of the receiver operating characteristic (ROC) curve. Furthermore, we demonstrate that a robotic arm can be reliably controlled using the proposed BCI system. This paper presents novel insights regarding the possibility of using the proposed MI-based BCI system in real-life applications.
A Novel 16-Channel Wireless System for Electroencephalography Measurements With Dry Spring-Loaded Sensors
(2014-06-01)
Liao, Lun-De
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Wu, Shang-Lin
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Liou, Chang-Hong
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Lu, Shao-Wei
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Chen, Shi-An
Understanding brain function using electroencephalography (EEG) is an important issue for cerebral nervous system diseases, especially for epilepsy and Alzheimer\'s disease. Many EEG measurement systems are used reliably to study these diseases, but their bulky size and the use of wet sensors make them uncomfortable and inconvenient for users. To overcome the limitations of conventional EEG measurement systems, a wireless and wearable multichannel EEG measurement system is proposed in this paper. This system includes a wireless data acquisition device, dry spring-loaded sensors, and a size-adjustable soft cap. We compared the performance of the proposed system using dry versus conventional wet sensors. A significant positive correlation between readings from wet and dry sensors was achieved, thus demonstrating the performance of the system. Moreover, four different features of EEG signals (i.e., normal, eye-blinking, closed-eyes, and teeth-clenching signals) were measured by 16 dry sensors to ensure that they could be detected in real-life cognitive neuroscience applications. Thus, we have shown that it is possible to reliably measure EEG signals using the proposed system. This paper presents novel insights into the field of cognitive neuroscience, showing the possibility of studying brain function under real-life conditions.
A Novel Mechanism to Fuse Various Sub-aspect Brain-computer Interface (BCI) Systems with PSO for Motor Imagery Task
(2015-01-01)
Lin, Chin-Teng
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Hsieh, Tsung-Yu
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Liu, Yu-Ting
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Wu, Shang-Lin
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Lin, Yang-Yin
In this study, we develop a novel multi-fusion brain-computer interface (BCI) system based on a fuzzy neural network (FNN) and information fusion approaches to cope with a classification task for identifying right/left hand motor imagery. In the proposed system, we utilize a filter bank and sub-band common spatial pattern (SBCSP) to extract features from raw EEG data. A self-organizing neural fuzzy inference network (SONFIN) is then applied for a recognition task. In order to improve the classification performance, we form a committee of networks and employ fuzzy integral (FI) to attain a joint decision. To further optimize the fusion approaches, a particle swarm optimization (PSO) algorithm is exploited to globally update parameters used in the fusion stage. In consequence, our experimental result shows that the proposed fuzzy fusion system possesses superior performance compared to other comparative models.
A TSV-Based Bio-Signal Package With mu-Probe Array
(2014-02-01)
Chou, Lei-Chun
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Lee, Shih-Wei
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Huang, Po-Tsang
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Chang, Chih-Wei
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Chiang, Cheng-Hao
Bio-signal probes providing stable observation with high quality signals are crucial for understanding how the brain works and how the neural signal transmits. Due to the weak and noisy characteristics of bio-signals, the connected interconnect length between the sensor and CMOS has significant impact on the bio-signal quality. In addition, long interconnections with wire bonding technique introduce noises and lead to bulky packaged systems. This letter presents an implantable through-silicon via (TSV) technology to connect sensors and CMOS devices located on the opposite sides of the chip for brain neural sensing applications. With the elimination of traditional wire bonding and packaging technologies, the quality of bio-signal can be greatly improved.
A TSV-Based Heterogeneous Integrated Neural-Signal Recording Device with Microprobe Array
(2014-01-01)
Chou, Lei-Chun
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Lee, Shih-Wei
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Cheng, Chuan-An
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Huang, Po-Tsang
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Chang, Chih-Wei
Highly integrated and miniaturized neural sensing microsystems are crucial for brain function investigation and neural prostheses realization. This paper presents a TSV-based heterogeneous integrated neural-signal recording device with microprobe array. By TSV, microprobe array and CMOS circuit make connection on the opposite sides of the chip. By measurement results on electrical characteristics of devices and TSV, this recording device is ready for bio-medical applications.
A Wireless Electrooculography-based Human-Computer Interface for Baseball Game
(2013-01-01)
Lin, Chin-Teng
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Wu, Shang-Lin
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Jiang, Wei-Ling
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Liang, Jyun-Wei
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Chen, Shi-An
Gaming control becomes popular based on the development of human-computer interface (HCI). Among many kinds of physiological signals, Electrooculography (EOG) signal is more stable which can be used to control HCI systems based on eye movement detection and signal processing methods. However, there are currently no effective multi-directional classification methods for monitoring eye movements. In addition, many EOG-based HCI systems have been developed with traditional wet electrodes. Those traditional electrodes require conductive gel and skin preparation on some users. Here, we describe a signal processing method used in a wireless EOG-based HCI system with dry electrodes for detecting eye movements to have 9 options. This system includes wireless EOG signal acquisition device, dry electrodes and an EOG signal processing algorithm. The EOG signal processing algorithm is based on 9 options of eye movement and blink signals. The results demonstrated an application of baseball game control using the proposed wireless HCI system. This system provides an effective and convenient method for eye movement detection.
An Advanced 2.5-D Heterogeneous Integration Packaging for High-Density Neural Sensing Microsystem
(2017-04-01)
Hu, Yu-Chen
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Huang, Yu-Chieh
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Huang, Po-Tsang
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Wu, Shang-Lin
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Chang, Hsiao-Chun
In the traditional neural sensing microstructure, the limited metal line pitch and the metal layer numbers restrict the neural signal routing ability from electrodes to circuit chips. Miniature packaging and excessive noise interference bottlenecks are some of the challenges faced by the electrodes and circuit chips integration with traditional wire bonding. This paper proposes a 2.5-D heterogeneous integration neural sensing microsystem based on the silicon substrate to overcome these issues. With standard semiconductor and 3-D integration processes, high-channel-density (256 channels at 25 mm(2)) neural sensing microsystem is achieved. Through silicon via provides the shortest vertical interconnection and dramatically minimizes the packaging. Furthermore, the interposer can carry multiple chips to enhance the function of the biosensor. Electrical characteristics and reliability examinations reveal its high quality and great performance as compared to traditional approaches. This novel highly integrated neural sensing microsystem is expected to contribute to the biomedical field for exploring and solving unknown biological mysteries.
An Implantable 128-Channel Wireless Neural-Sensing Microsystem using TSV-Embedded Dissolvable mu-Needle Array and Flexible Interposer
(2017-01-01)
Huang, Po-Tsang
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Huang, Yu-Chieh
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Wu, Shang-Lin
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Hu, Yu-Chen
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Lu, Ming-Wei
For implanted neural-sensing devices, one of the remaining challenges is to transmit stable power/data (P/D) transmission for high spatiotemporal resolution neural data. This paper presents a miniaturized implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable mu-needle array, a flexible interposer and 4 dies by 2.5D/3D TSV heterogeneous SiP technology. The 4 dies are 2 neural-signal acquisition ICs implemented by 90nm CMOS, 1 neural-signal processor by 40nm CMOS and 1 wireless P/D transmission circuitry by 0.18 mu m CMOS. Thus, the proposed wireless microsystem realizes 128-channel neural-signal sensing within the area of 5mm x 5mm, neural feature extraction and wireless P/D transmission using an on-interposer inductor. The overall average power of the circuits in this microsystem is only 9.85mW.