Browsing by Author "Wu, Sheng-Tsai"

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An RDL-First Fan-Out Panel-Level Package for Heterogeneous Integration Applications
(2019-01-01)
Lin, Yu-Min
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Wu, Sheng-Tsai
;
Wang, Chun-Min
;
Lee, Chia-Hsin
;
Huang, Shin-Yi
Technologies of Fan-outpanel-level packaging (FOPLP) are studies in this paper. First, the warpage control of a molded panel is a crucial problem for FOWLP technology development. In this paper, finite element analysis (FEA) is applied to study the influence of back end of the line (BEOL) process-induced warpage, as well as characterization for simulation, and investigation of each single process. In our process, a liquid release material is coated onto a 370 mm x 470 mm glass carrier. After baking, three layers of redistribution layer (RDL), passivation, and Cu leads are fabricated on the panel with coating, exposing, developing, lithography, and electroplating processes. Silicon test chips with a size of 16 mm x 10 mm and micro solder bumps with a pitch of 90 mu m are thinned down to 150 mu m. Test chips are then flip-chip bonded onto glass carrier with pre-bond and reflow proces. After panel molding, a laser debonding method, another key technology advancement, is utilized for panel debond. Debond performance, which is directly related to laser parameter and panel-level package (PLP) structure, is critical. After debonding, the molded panel is cleaned, followed by dicing and OSP coating processes, and then the electrical performance of the interconnection is evaluated. Reliability tests at the component level, such as pre-condition, thermal cycling test (TCT), and unbiased HAST (uHAST), are performed. The demonstration of RDL-first PLP technology without interposers proves its great potential in heterogeneous integration applications.
An RDL-First Fan-out Wafer-level Package for Heterogeneous Integration Applications
(2018-01-01)
Lin, Yu-Min
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Wu, Sheng-Tsai
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Shen, Wen-Wei
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Huang, Shin-Yi
;
Kuo, Tzu-Ying
Fan-out wafer-level packaging (FOWLP), a new heterogeneous integration technology, is gradually becoming an attractive solution. Compared with conventional 2.5D/3D IC structures, fan-out WLP does not use a costly interposer element and can have a thin, high-density, and low-cost IC packaging. In this study, a novel fan-out WLP with RDL-first method is demonstrated. Finite element method was used to optimize the warpage control of a reconstituted wafer and to identify the material properties and fabrication for the FOWLP. Calculation results were applied in the design of the test vehicle. Reliability testing of each component level was performed with different techniques such as temperature cycling test (TCT), high temperature storage (HTS) and thermal humidity storage test (THST). The demonstration of RDL-first WLP technology without interposer proves that it has excellent potential for heterogeneous integration applications.
Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology
(2018-08-01)
Shen, Wen-Wei
;
Lin, Yu-Min
;
Wu, Sheng-Tsai
;
Lee, Chia-Hsin
;
Huang, Shin-Yi
In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.