Browsing by Author "Wu, Shu-Hua"

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Investigation of Multi-V-th Efficiency for Trigate GeOI p-MOSFETs Using Analytical Solution of 3-D Poisson\'s Equation
(2015-01-01)
Wu, Shu-Hua
;
Yu, Chang-Hung
;
Chiang, Chun-Hsien
;
Su, Pin
;
電子工程學系及電子研究所
This paper provides an analytical subthreshold model for trigate MOSFETs with thin buried oxide (BOX) for multithreshold (multi-V-th) applications. This model shows a fairly good scalability in substrate bias and BOX thickness, which is crucial to the prediction of multi-Vth modulation through BOX. In addition, we demonstrate the application of our model in multi-V-th device design for trigate GeOI p-MOSFETs with the body-effect coefficient (gamma) over a wide range of design space efficiently examined. We have shown an enhanced multi-Vth modulation behavior in trigate GeOI p-MOSFETs. Our study indicates that, for a given subthreshold swing and gamma, the GeOI trigate p-MOSFET can possess a higher fin aspect ratio than the SOI counterpart.
New Findings on the Drain-Induced Barrier Lowering Characteristics for Tri-Gate Germanium-on-Insulator p-MOSFETs
(2015-11-01)
Wu, Shu-Hua
;
Yu, Chang-Hung
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper investigates the intrinsic drain-induced barrier lowering (DIBL) characteristics for tri-gate germanium-on-insulator (GeOI) p-MOSFETs through theoretical calculation by analytical solution of 3-D Poisson's equation corroborated with TCAD numerical simulation. It is found that, relative to the silicon-on-insulator counterpart, there exists a build-in negative substrate bias in the GeOI PFET. This built-in substrate bias, stemming mainly from the large discrepancy in bandgap between Ge and Si, pulls the carriers toward the channel/BOX interface and thus degrades the DIBL of the GeOI PFET beyond what permittivity predicts. This new mechanism has to be considered when designing or benchmarking tri-gate GeOI p-MOSFETs.
Stability of La(2)O(3) Metal-Insulator-Metal Capacitors under Constant Voltage Stress
(2010-01-01)
Wu, Shu-Hua
;
Deng, Chih-Kang
;
Hou, Tuo-Hung
;
Chiou, Bi-Shiou
;
電子工程學系及電子研究所
In this study, we demonstrate the stability of high-kappa La(2)O(3) metal-insulator-metal (MIM) capacitors under constant voltage stress (CVS). It was found that the variation in capacitance caused by CVS strongly depends on the injected charges regardless of stress biases. Furthermore, the quadratic voltage coefficient of capacitance (alpha) decreases with a logarithmic increase in dielectric loss. Charge trapping contributes to the relative capacitance variation under CVS while the reduced carrier mobility due to the stress-induced traps is responsible for the reduction of alpha. Additionally, high stability of 10-year lifetime is achieved for a 10-nm La(2)O(3) MIM capacitor with an 11.4 fF/mu m(2) capacitance density. (C) 2010 The Japan Society of Applied Physics
Stability of La2O3 Metal-Insulator-Metal Capacitors under Constant Voltage Stress
(2010-01-01)
Wu, Shu-Hua
;
Deng, Chih-Kang
;
Hou, Tuo-Hung
;
Chiou, Bi-Shiou
;
電子工程學系及電子研究所
In this study, we demonstrate the stability of high-kappa La2O3 metal-insulator-metal (MIM) capacitors under constant voltage stress (CVS). It was found that the variation in capacitance caused by CVS strongly depends on the injected charges regardless of stress biases. Furthermore, the quadratic voltage coefficient of capacitance (alpha) decreases with a logarithmic increase in dielectric loss. Charge trapping contributes to the relative capacitance variation under CVS while the reduced carrier mobility due to the stress-induced traps is responsible for the reduction of alpha. Additionally, high stability of 10-year lifetime is achieved for a 10-nm La2O3 MIM capacitor with an 11.4 fF/mu m(2) capacitance density. (C) 2010 The Japan Society of Applied Physics
Theoretical Investigation of DIBL Characteristics for Scaled Tri-Gate InGaAs-OI n-MOSFETs Including Sensitivity to Process Variations
(2017-01-01)
Wu, Shu-Hua
;
Yu, Chien-Lin
;
Yu, Chang-Hung
;
Su, Pin
;
電子工程學系及電子研究所
This paper investigates the intrinsic drain-induced barrier lowering (DIBL) characteristics of highly-scaled tri-gate n-MOSFETs with InGaAs channel based on ITRS 2021 technology node through numerical simulation corroborated with theoretical calculation. This paper indicates that, when studying short-channel effects in III-V FETs, one has to account for quantum-confinement, or else predictions will be pessimistic. Due to 2-D quantum-confinement, the DIBL of the InGaAs tri-gate devices can be significantly suppressed and be comparable to the Si counterpart. Besides, for highly-scaled InGaAs tri-gate NFETs, the impact of buried-oxide thickness on DIBL becomes minor, and the DIBL sensitivity to the fin-width and gate-length variations can also be suppressed by the quantum-confinement effect. This paper may provide insights for tri-gate device design using III-V high-mobility channel materials.