Browsing by Author "Wu, Tai-Bor"

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Advance in next Century nanoCMOSFET research
(2007-10-31)
Hwang, Huey-Liang
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Chiou, Yan-Kai
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Chang, Che-Hao
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Wang, Chen-Chan
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Lee, Kun-Yu
It is well known that Taiwan's IC industry is in the very leading front of the world, and production of 65 nm devices was launched in 2006. Within a few years, the need of high-k dielectrics and metal gates is eminent and truly indispensable. Professor H.L. Hwang (the author) organized 12 professors and 50 graduate students of National Tsing Hua University and Chiao Tung University, and executed this particular project, which is sponsored by the Ministry of Economic Affairs of Republic of China, and is aimed at treating efficiently this problem and transferred the critical technologies to industry in a time frame of 3 years. (C) 2007 Elsevier B.V. All rights reserved.
An oxide-buffered BE-MANOS charge-trapping device and the role of Al2O3
(2008)
Lai, Sheng-Chih
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Lue, Hang-Ting
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Liao, Chien-Wei
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Huang, Yu-Fong
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Yang, Ming-Jui
The role of Al2O3 in MANOS device is critically examined, and we conclude that its primary function is to reduce gate injection during erase operation. By itself, Al2O3 cannot stop charge leakage from the charge-trapping nitride layer. Furthermore, Al2O3 provides no magic during the erase operation, and MANOS erases very slowly through charge de-trapping. BE-SONOS [1], with the band engineered ONO tunneling layers, provides efficient channel hole injection for erase. BE-MANOS [2] should be an ideal combination with fast erase and good reliability. However, it shows poor data retention. By inserting a SiO2 buffer layer between Al2O3 and the SiN storage layer, the oxide-buffered BE-MANOS shows good performance and good reliability. The EOT scalability is also investigated.
Effect of bias stress on mechanically strained low temperature polycrystalline silicon thin film transistor on stainless steel substrate
(2009-07-27)
Peng, I-Hsuan
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Liu, Po-Tsun
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Wu, Tai-Bor
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光電工程學系
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顯示科技研究所
This paper reported the variation in performance of bias stressed low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) fabricated on metal foil substrate for flexible display applications. The mobility, threshold voltage (V(th)), and trap density (N(t)) of the proposed p-channel poly-Si TFT as a function of curvature radii were investigated. The significant increase in V(th) by 9% was observed as the compressive or tensile mechanical strain increases to 0.1%. In addition, the hole mobility increases by 7% due to an increased compressive strain of 0.1%, while hole mobility decreases by 3.5% with the increase in tensile strain of 0.1%. After dc bias stressing, the LTPS TFT with mechanical strain had better performance than that on flat state in both the mobility drop and V(th) shift. Mechanical strain influences the lattice arrangement and electric field at the drain electrode region that resisted device degradation in early stressing period.
Highly reliable MA BE-SONOS (Metal-Al2O3 bandgap engineered SONOS) using a SiO2 buffer layer
(2008)
Lai, Sheng-Chih
;
Lue, Hang-Ting
;
Liao, Chien-Wei
;
Wu, Tai-Bor
;
Yang, Ming-Jui
A Metal-high-K Bandgap-Engineered SONOS (MA BE-SONOS) with an additional SiO2 buffer layer is proposed. The thin SiO2 (5 similar to 6 nm) layer between the high-K (Al2O3) and nitride serves to prevent shallow trap generation. Contrary to the previously proposed MANOS or MA BE-SONOS devices using a simple high-k top dielectric, this composite structure eliminates the unstable high-K/nitride interface. Experimental results show that this new device can well suppress the erase saturation, just like MANOS. On the other hand, the data retention is greatly improved, owing to the much more stable interface between the nitride-trapping layer and top oxide. Very large memory window (> 7V) with excellent cycling endurance, read disturb immunity, and data retention has been successfully demonstrated. Theoretical model is also proposed to explain the principle of this device.