Browsing by Author "Wu, Tzu-Yun"

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A Comprehensive Modeling Framework for Ferroelectric Tunnel Junctions
(2019-01-01)
Huang, Hsin-Hui
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Wu, Tzu-Yun
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Chu, Yueh-Hua
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Wu, Ming-Hung
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Hsu, Chien-Hua
A modeling framework for ferroelectric tunnel junctions (FTJs) that considers nonpolar interfacial layers (ILs), multi-domain polarization, and complete ferroelectric/capacitive/tunneling currents simultaneously is proposed. This model explains both read and write operations including the controversial switching polarities of FTJ. We also provide useful guidelines for optimizing FTJ performance where the location of IL and the effective thickness ratio between ferroelectric and interfacial layers are found to be most critical.
Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design
(2018-05-01)
Liu, Jen-Chieh
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Wu, Tzu-Yun
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Hou, Tuo-Hung
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電機學院
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College of Electrical and Computer Engineering
A device-circuit co-design strategy of incremental step pulse programming (ISPP) tailored specifically for resistive-switching random access memory (RRAM) is elaborated using HfO2 RRAM as an example. The proposed strategy optimizes ISPP by considering programming energy, speed, peripheral circuit design, and device lifetime simultaneously. Interplay between ISPP configuration and device switching behavior is comprehensively clarified, and the result provides useful indicators for estimating peripheral circuit overhead and programming performance. Overstress effects affect both switching voltages and endurance lifetime substantially and, thus, should be carefully minimized.
Sub-nA Low-Current HZO Ferroelectric Tunnel Junction for High-Performance and Accurate Deep Learning Acceleration
(2019-01-01)
Wu, Tzu-Yun
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Huang, Hsin-Hui
;
Chu, Yueh-Hua
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Chang, Chih-Cheng
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Wu, Ming -Hung
This paper presents a unique opportunity of HZO ferroelectric tunnel junction (FTJ) for in-memory computing. The device operates at an extremely low sub-nA current while simultaneously achieving 50-ns fast switching, > 10(7) cycling endurance, > 10-yr retention, minimal variability, and analog state modulation. We analyze an FTJ-based deep binary neural network. It achieves better accuracy and remarkable 702, 101, and 7 x 10(4) times improvements in power, area, and energy area product efficiency compared with those using NVMs with a typical mu A cell current designed for fast memory access.