Browsing by Author "Wu, WH"

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Barrier characteristics of PECVD alpha-SiC : H dielectrics
(2001)
Chiang, CC
;
Wu, ZC
;
Wu, WH
;
Chen, MC
;
Ko, CC
This work investigates the thermal stability and barrier characteristics of three species of PECVD alpha-SiC:H dielectric films with dielectric constants between 3.5 and 5.4. It is found that the dielectric constant decreases with increasing content of carbon in the alpha-SiC:H film. All of the three specie's of alpha-SiC:H films are thermally stable at temperatures of up to 500degreesC. However, degraded barrier capability and moisture resistance were observed for the alpha-SiC:H film with a k value around 3.5, which has a C/Si atomic ratio of 0.875. This is presumably attributed to poorly crosslinked molecular structure and porosity enhancement by the abundant amount of carbon in the alpha-SiC:H film.
Comparative study of physical and electrical characteristics of F- and C-doped low-K CVD oxides
(2001)
Wu, ZC
;
Shiung, ZW
;
Chiang, CC
;
Wu, WH
;
Chen, MC
This work makes a comparative study of physical and electrical properties between two species of inorganic low-K CVD oxides, namely F-doped FSG (fluorinated silicate glass, K=3.5) and C-doped OSG (organosilicate glass, K=2.9). It is found that FSG has a higher thermal stability (>600degreesC) than OSG (500degreesC) based on the results of 30 min thermal anneal in N-2 ambient. The degradation of the low-K property in OSG is predominately due to the thermal decomposition of methyl (CH3) groups at temperatures above 500degreesC, which are incorporated to reduce the density and polarizability of OSG. For the Cu-gated oxide-sandwiched low-K dielectric MIS capacitors, Cu permeation was observed in both FSG and OSG after the MIS capacitors were subjected to bias-temperature stressing (BTS) at 250 and 150degreesC, respectively, with an effective applied field of 0.8 MV/cm. It appeared that Cu drifted more readily in OSG than in FSG presumably because OSG has a more porous and less dense structure than FSG. The Cu penetration can be efficiently mitigated by a thin nitride dielectric barrier layer.
Dielectric and barrier properties of spin-on organic aromatic low dielectric constant polymers FLARE and SiLK
(2001-06-01)
Wu, ZC
;
Shiung, ZW
;
Wu, RG
;
Liu, YL
;
Wu, WH
This work investigates the dielectric and barrier properties of two species of organic aromatic low dielectric constant (low-k) polymers, namely, FLARE and SiLK. Experimental results indicate that both of the low-k polymers exhibit acceptable thermal stability with respect to a thermal annealing at 400 degreesC for 8 h in an N-2 ambient. Moreover, they show a good dielectric barrier property against Cu penetration under bias-temperature stressing (BTS) at 150 degreesC with an applied effective field of 0.8 MV/cm. Nevertheless, an anomalous instability of the capacitance-voltage curve was observed for the first time under BTS. This finding is explained by the proposed model of stress induced dielectric polarization charges within these organic aromatic polymers. The polarization instability may seriously degrade the long term reliability of circuit operations. (C) 2001 The Electrochemical Society.
Effects of base oxide in HfSiO/SiO2 high-k gate stacks
(2004)
Wu, WH
;
Chen, MC
;
Wang, MF
;
Hou, TH
;
Yao, LG
Electrical characteristics of HfSiO/SiO2 high-k gate stacks have been extensively explored with regard to the effects of base oxide. The flatband voltage shift in N/PMOS capacitors is independent of base oxide thickness, and the dielectric breakdown of the gate stacks is determined by base oxide. In addition, base oxide thickness has a great impact on device performance and charge trapping, presumably due to remote Coulomb scattering (RCS) in the HfSiO bulk layer and direct tunneling through the base oxide. Threshold voltage instability induced by charge trapping will be a major reliability concern for Hf-based high-k gate dielectrics in the future.
Effects of base oxide thickness and silicon composition on charge trapping in HfSiO/SiO(2) high-k gate stacks
(2005-08-01)
Wu, WH
;
Chen, MC
;
Tsui, BY
;
How, YT
;
Yao, LG
This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO(2) high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf-OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO(2) high-k gate stacks.
Effects of base oxide thickness and silicon composition on charge trapping in HfSiO/SiO2 high-k gate stacks
(2005-08-01)
Wu, WH
;
Chen, MC
;
Tsui, BY
;
How, YT
;
Yao, LG
This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO2 high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf-OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO2 high-k gate stacks.
Formation of NiSi-silicided p(+)n shallow junctions by BF(2)(+) implantation into/through silicide and rapid thermal annealing
(2005-01-01)
Wang, CC
;
Wu, YK
;
Wu, WH
;
Chen, MC
;
電子工程學系及電子研究所
NiSi-silicided p(+) n shallow junctions are fabricated by BF(2)(+) implantation into/through a thin NiSi silicide layer, followed by rapid thermal annealing (RTA). The NiSi film starts to show agglomeration after RTA at 650degreesC, which may result in the formation of discontinuous islands at higher temperatures. The incorporation of fluorine atoms in the NiSi film can retard the film agglomeration making the film stable up to 800degreesC. A forward ideality factor very close to unity and a reverse bias current density of 0.6 nA/cm(2) can be attained for the NiSi(31 nm)/p(+)n junctions fabricated by BF(2)(+) implantation to a dose of 5 x 10(15) cm(-2) at 35 keV, followed by RTA for 30 s at 650degreesC; the junction formed is about 37 nm measured from the NiSi/Si interface. Activation energy measurement shows that the reverse bias junction currents are dominated by the diffusion current, which indicates that most of the implanted damage can be recovered by RTA at temperatures as low as 650degreesC.
Formation of NiSi-silicided p(+)n shallow junctions by BF2+ implantation into/through silicide and rapid thermal annealing
(2005-01-01)
Wang, CC
;
Wu, YK
;
Wu, WH
;
Chen, MC
;
電子工程學系及電子研究所
NiSi-silicided p(+) n shallow junctions are fabricated by BF2+ implantation into/through a thin NiSi silicide layer, followed by rapid thermal annealing (RTA). The NiSi film starts to show agglomeration after RTA at 650degreesC, which may result in the formation of discontinuous islands at higher temperatures. The incorporation of fluorine atoms in the NiSi film can retard the film agglomeration making the film stable up to 800degreesC. A forward ideality factor very close to unity and a reverse bias current density of 0.6 nA/cm(2) can be attained for the NiSi(31 nm)/p(+)n junctions fabricated by BF2+ implantation to a dose of 5 x 10(15) cm(-2) at 35 keV, followed by RTA for 30 s at 650degreesC; the junction formed is about 37 nm measured from the NiSi/Si interface. Activation energy measurement shows that the reverse bias junction currents are dominated by the diffusion current, which indicates that most of the implanted damage can be recovered by RTA at temperatures as low as 650degreesC.
Leakage mechanism in Cu damascene structure with methylsilane-doped low-K CVD oxide as intermetal dielectric
(2001-06-01)
Wu, ZC
;
Chiang, CC
;
Wu, WH
;
Chen, MC
;
Jeng, SM
This letter investigates the leakage mechanism in the Cu damascene structure with methylsilane-doped low-k CVD organosilicate glass (OSG) as the intermetal dielectric (IMD), The leakage between Cu lines was found to be dominated by the Frenkel-Poole (F-P) emission in OSG for the structure using a 50-nm SiC etching stop layer (ESL), In the structure using a 50-nm SiN ESL, the leakage component through SiN also made a considerable contribution to the total leakage in addition to the bulk leakage from trapped electrons in OSG, An appropriate ESL of sufficient thickness is essential to reduce the leakage through the ESL if an ESL is used in the Cu damascene integration scheme.
Physical and barrier properties of plasma enhanced chemical vapor deposition alpha-SiC : N : H films
(2003-07-01)
Chiang, CC
;
Wu, ZC
;
Wu, WH
;
Chen, MC
;
Ko, CC
In this work, we investigate the thermal stability and physical and barrier properties of three species of plasma enhanced chemical vapor deposition (PECVD) alpha-SiC:N:H silicon carbide films with different carbon and nitrogen contents and dielectric constants less than a value of 5.5. For comparison, one species of alpha-SiN:H film with a k value of 7.2 is also studied. It is found that the dielectric constant decreases with increasing content of carbon and decreasing content of nitrogen in the alpha-SiC:N:H film. All of the three species of alpha-SiC:N:H and the one species of alpha-SiN:H films are thermally stable at temperatures up to 500degreesC. However, degraded barrier capability and moisture resistance were observed for the alpha-SiC:N:H film with a k value of 3.5, which has a C/Si atomic ratio of 0.875. This is presumably due to the poorly crosslinked molecular structure and porosity enhancement caused by the abundant amount of carbon in the alphaSiC:N:H film.
Physical and electrical characteristics of F- and C-doped low dielectric constant chemical vapor deposited oxides
(2001-06-01)
Wu, ZC
;
Shiung, ZW
;
Chiang, CC
;
Wu, WH
;
Chen, MC
This work compares the physical and electrical properties of two species of inorganic low dielectric constant (low-k) chemical vapor deposited (CVD) oxides, F-doped fluorinated silicate glass (FSG, k = 3.5) and C-doped organosilicate glass (OSG, k = 2.9). Experimental results indicate that FSG has a higher thermal stability >600 degreesC! than OSG (500 degreesC), based on the results of thermal annealing for 30 min in an N-2 ambient. The degradation of the low-k property in OSG is mainly due to the thermal decomposition of methyl (-CH3) groups at temperatures above 500 degreesC. For the Cu gated oxide-sandwiched low-k dielectric metal-insulator-semiconductor (MIS) capacitors, Cu penetration was observed in both FSG and OSG after the MIS capacitors were bias-temperature stressed at 250 and 150 degreesC, respectively, with an effective applied field of 0.8 MV/cm. Specifically, Cu appeared to drift more readily in OSG than in FSG, presumably because OSG has a more porous and less dense structure than FSG. The Cu permeation can be impeded by a thin nitride (SiN) barrier layer. (C) 2001 The Electrochemical Society.
Physical and electrical characteristics of methylsilane- and trimethylsilane-doped low dielectric constant chemical vapor deposited oxides
(2001-06-01)
Wu, ZC
;
Shiung, ZW
;
Chiang, CC
;
Wu, WH
;
Chen, MC
This work investigates the physical and electrical properties of two species of inorganic C-doped low dielectric constant (low-k) chemical vapor deposited (CVD) organosilicate glasses (OSGs, alpha -SiCO:H). They are both deposited by plasma-enhanced CVD (PECVD) processes using methylsilane [(CH3)SiH3, 1 MS]- and trimethylsilane [(CH3)(3)SiH, 3 MS]-based gases as the reagents, and are designated as OSG1 and OSG2, respectively. Experimental results indicate that the thermal stability temperature of OSG1 is 500 degreesC, while that of OSG2 is 600 degreesC, based on the results of thermal annealing for 30 min in an N-2 ambient. The deterioration of the low-k property in OSG1 is predominately due to the thermal decomposition at temperatures above 500 degreesC of methyl (-CH3) groups, which are introduced to lower the density and polarizability of OSGs. For the Cu-gated oxide-sandwiched low-k dielectric metal-insulator-semiconductor (MIS) capacitors, Cu permeation was observed in both OSG1 and OSG2 after the MIS capacitors were bias-temperature stressed at 150 degreesC with an effective applied field of 0.8 MV/cm. Moreover, Cu appeared to drift more readily in OSG1 than in OSG2, presumably because OSG1 has a more porous and less cross-linked structure than OSG2. The Cu penetration can be mitigated by a thin nitride dielectric barrier. (C) 2001 The Electrochemical Society.
Two-frequency C-V correction using five-element circuit model for high-k gate dielectric and ultrathin oxide
(2006-05-01)
Wu, WH
;
Tsui, BY
;
Huang, YP
;
Hsieh, FC
;
Chen, MC
A new circuit model of -five elements has been proposed for the two-frequency capacitance-voltage (C-V) correction of high-k gate dielectric and ultrathin oxide. This five-element circuit model considered the static and dynamic dielectric losses in a lossy MOS capacitor, the parasitic well/substrate resistance, and the series inductance in the cables and probing system. Each of the circuit elements could be easily extracted from the two-frequency C-V and static current-voltage (I-V) measurements if some criteria are well satisfied. In addition, this model can also be transformed into another two four-element circuit models to simplify the analysis and calculations, depending on the gate ea age current.