Browsing by Author "Wu, Wei-Cheng"

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60 GHz broadband Ms-to-CPW hot-via flip chip interconnects
(2007-11-01)
Wu, Wei-Cheng
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Hsu, Li-Han
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Chang, Edward Yi
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Kaernfelt, Camilla
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Zirath, Herbert
In this letter, the microstrip-to-coplanar waveguide (MS-to-CPW) hot-via flip chip interconnect has been experimentally demonstrated to have broadband performance from dc to 67 GHz. The interconnect structures with the hot-via transitions were first designed and optimized by using the electromagnetic simulation tool. Three types of designs were investigated in this letter. The interconnect structures were then fabricated and radio frequency (RF) tested up to 67 GHz. The optimized interconnect structure with the compensation design demonstrated excellent RF characteristics with the insertion loss less than 0.5 dB and the return loss below 18 dB over a very broad bandwidth from dc to 67 GHz. This is to our knowledge the best result reported for this frequency range.
A delta-doped InGaP/InGaAs pHEMT with different doping profiles for device-linearity improvement
(2007-07-01)
Lin, Yueh-Chin
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Chang, Edward Yi
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Yamaguchi, Hiroshi
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Wu, Wei-Cheng
;
Chang, Chun-Yen
In this paper, delta-doped InGaP/InGaAs pseudomorphic high-electron-mobility transistors (pHEMTs) with doping-profile modifications are investigated in order to improve the device linearity. The proposed modification was based on the third-order intermodulation distortion (IM3) and the third-order intercept point (IP3) analysis using a simple equivalent circuit of the devices. The correlations of the extrinsic transconductance (Gm) with IM3 and IP3 indicate that the flatness of Gin, as a function of gate-bias causes a lower IM3 level. On the other hand, a high Gm with a flatter Gm distribution results in higher IP3 value for the device. Therefore, doping modifications that improve the flatness of the Gm distribution will also improve the device linearity. Doping modifications in the Schottky layer (Schottky layer doped) and in the channel layer (channel doped) of the conventional delta-doped InGaP/InGaAs pHEMT were investigated. It was also found that extra doping, either in the channel region or in the Schottky layer, improved the flatness of the Gm distribution under different gate-bias conditions. This achieved a lower IM3 and a higher IP3 with a small sacrifice in the peak Gm value. The power performances of these devices were tested at different drain biases. Even though it had the lowest electron mobility among the three different types of devices studied, the channel-doped device demonstrated the best overall linearity performance, the highest IP3 value, the lowest IM3 level, and the best adjacent-channel power ratio under code-division multiple-access modulation.
Design and Fabrication of 0/1-Level RF-Via Interconnect for RF-MEMS Packaging Applications
(2010-02-01)
Hsu, Li-Han
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Wu, Wei-Cheng
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Chang, Edward Yi
;
Zirath, Herbert
;
Wu, Yun-Chi
This paper presents the parametric study of RF-via (0-level) and flip-chip bump (1-level) transitions for applications of packaging coplanar RF-MEMS devices. The key parameters were found to be the bumps' and vias' positions and the overlap of the metal pads, which should be carefully considered in the entire two levels of packages. The length of the backside transmission line, determining the MEMS substrate area, showed minor influence on the interconnect performance. With the experimental results, the design rules have been developed and established. The optimized interconnect structure for the two levels of packages demonstrates the return loss beyond 15 dB and the insertion loss within 0.6 dB from dc to 60 GHz.
Design of Flip-Chip Interconnect Using Epoxy-Based Underfill Up to V-Band Frequencies With Excellent Reliability
(2010-08-01)
Hsu, Li-Han
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Wu, Wei-Cheng
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Chang, Edward Yi
;
Zirath, Herbert
;
Hu, Yin-Chu
This study demonstrates a flip-chip interconnect with epoxy-based underfill (epsilon(r) = 3.5 and tan delta = 0.02 at 10 MHz) for packaging applications up to V-band frequencies. To achieve the best interconnect performance, both the matching designs on GaAs chip and Al(2)O(3) substrate were adopted with the underfill effects taken into consideration. The optimized flip-chip interconnect showed excellent performance from dc to 67 GHz with return loss below -20 dB and insertion loss less than 0.6 dB. Furthermore, the dielectric loss induced by the underfill was extracted from measurement and compared with the simulation results. The reliability tests including 85 degrees C/85 % relative humidity test, thermal cycling test, and shear force test were performed. For the first time, the S-parameters measurement was performed to check the flip-chip reliability, and no performance decay was observed after 1000 thermal cycles. Moreover, the mechanical strength was improved about 12 times after the underfill was applied. The results show that the proposed flip-chip architecture has excellent reliability and can be applied for commercial applications.
Design, Fabrication, and Characterization of Novel Vertical Coaxial Transitions for Flip-Chip Interconnects
(2009-05-01)
Wu, Wei-Cheng
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Chang, Edward Yi
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Hwang, Ruey-Bing
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Hsu, Li-Han
;
Huang, Chen-Hua
In this paper, a novel transition design using vertical "coaxial transition" for coplanar waveguide (CPW-to-CPW) flip-chip interconnect is proposed and presented for the first time. The signal continuity is greatly improved since the coaxial-type transition provides more return current paths compared to the conventional transition in the flip-chip structure. The proposed coaxial transition structure shows a real coaxial property from the 3-D electromagnetic wave simulation results. The design rules for the coaxial transition are presented in detail with the key parameters of the coaxial transition structure discussed. For demonstration, the back-to-back flip-chip interconnect structures with the vertical coaxial transitions have been successfully fabricated and characterized. The demonstrated interconnect structure using the coaxial transition exhibits the return loss below 25 dB and the insertion loss within 0.4 dB from dc to 40 GHz. Furthermore, the measurement and simulation results show good agreement. The novel coaxial transition demonstrates excellent interconnect performance for flip-chip interconnects and shows great potential for flip-chip packaging applications at millimeter waves.
Design, Fabrication, and Reliability of Low-Cost Flip-Chip-On-Board Package for Commercial Applications up to 50 GHz
(2012-03-01)
Hsu, Li-Han
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Oh, Chee-Way
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Wu, Wei-Cheng
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Chang, Edward Yi
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Zirath, Herbert
This paper presents a flip-chip-on-board (FCOB) packaging technology using a Rogers RO3210 laminate for microwave applications. Compared to the conventional microwave packaging architecture, the proposed FCOB technology skips one level of the ceramic package and thus results in lower reflections and manufacturing costs. To fulfill the small dimension requirement on printed circuit boards, the coplanar waveguide (CPW) transmission line and flip-chip bump were fabricated on a high-k RO3210 board (epsilon(r) = 10.2) with photolithography and electroplating. The GaAs chip patterned with the CPW line was then flip-chip-mounted onto the RO3210 laminate board. This structure displayed excellent performance from dc to 50 GHz with a return loss S-11 greater than 18 dB and insertion loss S-21 less than 0.5 dB. Meanwhile, the flip-chip bonding of the in-house-fabricated In0.52Al0.As-48/In0.6Ga0.4As metamorphic high-electron-mobility transistor devices on RO3210 also displayed excellent gain performance with a small degradation of 1 dB from dc to 40 GHz, showing the potential of implementing microwave integrated circuits on RO3210. To enhance the mechanical reliability, an epoxy-based underfill was injected into the flip-chip assemblies. Thermal cycling tests were performed to test the interconnect reliability, and the results indicated that the samples passed the thermal cycling test at least up to 600 cycles, showing excellent reliability for commercial applications. To the best of the authors' knowledge, this is the first study that evaluates the use of the RO3210 laminate for microwave flip-chip in open literature.
High Frequency Flip Chip Package Process of Polymer Substrate and Structure thereof
(2010-09-30)
Chang, Edward-yi
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Hsu, Li-Han
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Oil, Chee-Way
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Wu, Wei-Cheng
;
Wang, Chin-te
In a high frequency flip chip package process of a polymer substrate and a structure thereof, the structure is a one-layer structure packaged by a high frequency flip chip package process to overcome the shortcomings of a conventional two-layer structure packaged by the high frequency flip chip package process. The conventional structure not only incurs additional insertion loss and return loss in its high frequency characteristic, but also brings out a reliability issue. Thus, the manufacturing process of a ceramic substrate in the conventional structure still has the disadvantages of a poor yield rate and a high cost.
Investigation of the Flip-Chip Package With BCB Underfill for W-Band Applications
(2014-01-01)
Wang, Chin-Te
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Hsu, Li-Han
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Wu, Wei-Cheng
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Hsu, Heng-Tung
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Chang, Edward Yi
Flip-chip package has great potential for use in millimeter-wave applications. However, the coefficient of thermal expansion mismatch between the chip and the substrate usually generates thermal stresses that fracture the flip-chip structure. The use of underfills with low dielectric loss is essential to improve the mechanical strength and reliability of the flip-chip package. Benzocyclobutene (BCB) was used in this study as the underfill material for the flip-chip structure using the no-flow process. The flip-chip structure with BCB injection provides good RF performance with a return loss of better than 18 dB and an insertion loss of 0.6 dB up to 100 GHz, in addition to a lower dielectric loss. Furthermore, thermal cycle and shear force tests show that the underfill injection can significantly improve the reliability of a flip-chip package.
Vertical Transmission Structure
(2009-10-29)
Chang, Edward Yi
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Wu, Wei-Cheng
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Hwang, Ruey-Bing
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Hsu, Li-Han
A vertical transmission structure for high frequency transmission lines includes a conductive axial core and a conductive structure surrounding the conductive axial core. The vertical transmission structure is applied to a high-frequency flip chip package for reducing the possibility of underfill from coming in contact with the conductive axial core.