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Browsing by Author "Wu, Wei-Hsuan"

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    A 794Mbps 135mW Iterative Detection and Decoding Receiver for 4x4 LDPC-Coded MIMO Systems in 40nm
    (2015)
    Wu, Wei-Hsuan
    ;
    Sun, Wei-Cheng
    ;
    Yang, Chia-Hsiang
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    Ueng, Yeong-Luh
    ;
    交大名義發表
    A low-density parity-check (LDPC)-coded multiple-input multiple-output (MIMO) systems with iterative detection and decoding (IDD) chip is integrated in 1.33mm(2) in 40nm CMOS. The maximum gross throughput is 794Mb/s for a 4x4 16-QAM configuration at 288MHz. The chip dissipates 135mW at 0.9V, achieving an energy efficiency of 170pJ/bit. Compared to non-IDD receivers, composed of state-of-the art MIMO detectors and LDPC decoders, this work achieves even higher area and energy efficiencies, despite the improved error performance.