Browsing by Author "Wu, Woei-Cherng"

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A highly reliable multi-level and 2-bit/cell operation of wrapped-select-gate (WSG) SONOS memory with optimized ONO thickness
(2007)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
;
Wang, Jer-Chyi
High-performance wrapped-select-gate (WSG) SONOS (silicon-oxide-nitride-silicon) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism with different ONO thickness in WSG-SONOS memory was well investigated. The different programming efficiency of the WSG-SONOS memory with different ONO thickness can be explained by the lateral electrical field extracted from the simulation. Furthermore, multi-level storage is easily obtained and well V-th distribution is also presented. High program/erase speed (10us/5ms) and low programming current (3.5uA) are performed to achieve the multi-level operation with excellent gate and drain disturbance, second-bit effect, data retention and endurance.
Characteristics of HfO(2)/Poly-Si Interfacial Layer on CMOS LTPS-TFTs With HfO(2) Gate Dielectric and O(2) Plasma Surface Treatment
(2008-12-01)
Ma, Ming-Wen
;
Chiang, Tsung-Yu
;
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Lei, Tan-Fu
In this paper, high-performance complementary-metal-oxide-semiconductor low-temperature polycrystalline-silicon thin-film transistors (CMOS LTPS-TFTs) with HfO(2) gate dielectric are fabricated on one wafer for the first time. Low threshold voltage and excellent subthreshold swing can be achieved simultaneously for N- and P-channel LTPS-TFTs without hydrogenation. In addition, the impacts of the HfO(2)/poly-Si interfacial layer on N- and P-channel LTPS-TFTs are also specified. In order to enhance the characteristics of HfO(2) LTPS-TFT further, oxygen plasma surface treatment is employed to improve the interface quality and passivate the defects of channel grain boundaries, thus increasing the carrier mobility and reducing the phonon scattering. The CMOS LTPS-TFTs with HfO(2) gate dielectric and oxygen plasma treatment would be suitable for the application of system-on-panel.
Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-kappa gate dielectric
(2008-02-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Wu, Yi-Hong
In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are well investigated for the first time. Under room temperature stress condition, the PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for HfO2 LTPS-TFT. In addition, an abnormal behavior of the I-min degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of device's performance under high-temperature stress condition can be attributed to the damages of both the HfO2 gate dielectric and the poly-Si grain boundaries.
High-performance metal-induced laterally crystallized polycrystalline silicon p-channel thin-film transistor with TaN/HfO2 gate stack structure
(2008-06-01)
Ma, Ming-Wen
;
Chao, Tien-Sheng
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Kao, Kuo-Hsing
In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateral-crystallization (MILC) channel layer and TaN/HfO2 gate stack is demonstrated for the first time. The devices of low threshold voltage V-TH similar to 0.095 V, excellent subthreshold swing S.S. similar to 83 mV/dec., and high field-effect mobility mu(FE) similar to 240 cm(2)/V center dot s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO2 gate dielectric with the effective oxide thickness of 5.12 mn.
High-Reliability Dynamic-Threshold Source-Side Injection for 2-Bit/Cell With MLC Operation of Wrapped Select-Gate SONOS in NOR-Type Flash Memory
(2010-09-01)
Wang, Kuan-Ti
;
Chao, Tien-Sheng
;
Wu, Woei-Cherng
;
Yang, Wen-Luh
;
Lee, Chien-Hsing
For the first time, a high-performance (tau(PGM) = 200 ns/tau(ERS) = 5 ms) cell with superior reliability characteristics is demonstrated in a NOR-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate silicon-oxide-nitride-oxide-silicon memory device, with multilevel and 2-bit/cell operation. Using DTSSI enables easy extraction of the multilevel states with a tight V(TH) distribution, a nearly negligible second-bit effect, superior endurance characteristics, and good data retention.
High-Speed Multilevel Wrapped-Select-Gate SONOS Memory Using a Novel Dynamic Threshold Source-Side-Injection (DTSSI) Programming Method
(2009-06-01)
Wang, Kuan-Ti
;
Chao, Tien-Sheng
;
Wu, Woei-Cherng
;
Chiang, Tsung-Yu
;
Wu, Yi-Hong
A. high programming speed with a low-power-consumption wrapped-select-gate poly-Si-oxide-nitride-oxide-silicon memory is successfully demonstrated using the novel dynamic threshold source-side-injection programming technique. The select gate embedded in such particular memory structure acts like a dynamic MOSFET resulting in programming current (I(PGM)) that can be enhanced in this DT mode, easily attaining a high programming speed of about 100 ns. It still doubles the memory density by achieving the 2-bit/cell operation with MLC under DT mode.
Highly reliable multilevel and 2-bit/cell operation of wrapped select gate (WSG) SONOS memory
(2007-03-01)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
;
Wang, Jer-Chyi
In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multilevel and 2-bit/cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mu s/5 ms) and low programming current (3.5 mu A) for our WSG SONOS by a source-side injection. Besides the excellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (> 150 degrees C) and good endurance (> 10(4)) are also presented. This novel WSG-SONOS memory with a multilevel and 2-bit/cell operation can be used in future high-density and high-performance memory application.
Impact of high-k offset spacer in 65-nm node SOI devices
(2007-03-01)
Ma, Ming-Wen
;
Wu, Chien-Hung
;
Yang, Tsung-Yu
;
Kao, Kuo-Hsing
;
Wu, Woei-Cherng
In this letter, 65-nm node silicon-on-insulator devices with high-k, offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-k, offset spacer dielectric can effectively increase the ON-state driving current I-ON and reduce the OFF leakage current I-OFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the I-ON/I-OFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-k offset spacer dielectric.
Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-kappa LTPS-TFT
(2008-02-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Wu, Yi-Hong
In this letter, fluorine ion implantation with low-temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO2 low-temperature poly-Si thin-film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of I-min is achieved because 25% grain-boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO2 gate dielectric and fluorine preimplantation can simultaneously achieve low V-TH similar to 1.32 V, excellent subthreshold swing similar to 0.141 V/dec, and high I-ON/I-min current ratio 1.98 x 10(7).
Impacts of N-2 and NH3 Plasma Surface Treatments on High-Performance LTPS-TFT With High-kappa Gate Dielectric
(2008-11-01)
Ma, Ming-Wen
;
Chao, Tien-Sheng
;
Chiang, Tsung-Yu
;
Wu, Woei-Cherng
;
Lei, Tan-Fu
Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high-kappa gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility mu(FE) improvements of similar to 86.0% and 112.5% are observed for LTPS-TFTs with HfO2 gate dielectric after N-2 and NH3 plasma surface treatments, respectively. In addition, the N2 and NH3 plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility mu(FE) at high gate bias voltage V-G, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage V-TH similar to 0.33 V, excellent subthreshold swing S.S. similar to 0.156 V/decade, and high field-effect mobility mu(FE) similar to 62.02 cm(2) /V . s would be suitable for the application of system-on-panel.
Improvement on performance and reliability of TaN/HfO2 LTPS-TFTs with fluorine implantation
(2008-03-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Yang, Tsung-Yu
In this paper, we demonstrate the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with TaN metal-gate and HfO2 gate dielectric to achieve high performance characteristics. A high performance LTPS-TFT with low threshold voltage 0.9 V, excellent subthreshold swing 0.15 V/decade and high I-on/I-min current ratio 1.9 x 10(6) are derived without any hydrogen treatment. In addition, we also introduce the fluorine implantation prior to the Si thin-film crystallization to passivate the defects in grain-boundaries of the channel film and HfO2/polysilicon interface. Significant improvements on subthreshold swing and I-min are observed. In addition, the transconductance degradation and threshold voltage instability due to hot carrier stress is also investigated, respectively. Finally, we derive a high reliability and performance LTPS-TFT with low threshold voltage similar to 1.38 V, ultra-low subthreshold swing 0.132 V/decade and high I-on/I-min current ratio 1.21 x 10(7), which is suitable for the application of system-on panel (SOP). (c) 2007 Elsevier Ltd. All rights reserved.
Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory
(2008-01-01)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
;
Chen, Jian-Hao
In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good V(TH) distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 mu s/5 ms) and low programming current (3.5 mu A) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.
Performance and interface characterization for contact etch stop layer-strained nMOSFET with HfO2 gate dielectrics under pulsed-IV measurement
(2008)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Chiu, Te-Hsin
;
Wang, Jer-Chyi
;
Lai, Chao-Sung
In this paper, high-performance contact etching stop layer (CESL)-strained n-metal-oxide-semiconductor field effect transistor (nMOSFET) with HfO2 gate dielectrics has been successfully demonstrated. The effects of the CESL layer to the high-k without trapping behaviors are investigated by the pulse current-voltage (IV) technique for the first time. It is found that a roughly 55 and 60% increase of mobility and I-ON, respectively, can be achieved for the 300 nm CESL HfO2 nMOSFET using pulsed-IV measurement. Furthermore, a superior HfO2/Si interface for CESL devices is observed, demonstrated by an obvious interface state density reduction (6 x 10(11)-9 x 10(10) cm(-2)).
Performance enhancement for strained HfO(2) nMOSFET with contact etch stop layer (CESL) under pulsed-IV measurement
(2007)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Chiu, Te-Hsin
;
Wang, Jer-Chyi
;
Lai, Chao-Sung
High-performance CESL strained nMOSFET with HfO(2) gate dielectrics has been successfully demonstrated in this work. It is found that, the transconductance (g(m)) and driving current (I(on)) of the nMOSFETs increase 70% and 90%, respectively, of the increase of devices with a 300 nm capping nitride layer. A superior HfO(2)/Si interface for CESL-devices is observed, demonstrated by an obvious interface state density reduction (6.56x10(11) to 9.85x10(10) cm(-2)). Further, a roughly 50% and 60% increase of g(m) and I(on), respectively, can be achieved for the 300 nm SiN-capped HfO(2) nMOSFET without considering charge trapping under pulsed-IV measurement.
Physical Mechanism of High-Programming-Efficiency Dynamic-Threshold Source-Side Injection in Wrapped-Select-Gate SONOS for NOR-Type Flash Memory
(2009-11-01)
Wang, Kuan-Ti
;
Chao, Tien-Sheng
;
Chiang, Tsung-Yu
;
Wu, Woei-Cherng
;
Kuo, Po-Yi
For the first time, a programming mechanism for conventional source-side injection (SSI) (normal mode), substrate-bias enhanced SSI (body mode), and dynamic-threshold SSI (DTSSI) (DT mode) of a wrapped-select-gate SONOS memory is developed with 2-D Poisson equation and hot-electron simulation and programming characteristic measurement for NOR Flash memory. Compared with traditional SSI, DTSSI mechanisms are determined in terms of lateral acceleration electric field and programming current (I(PGM)) in the neutral gap region, resulting in high programming efficiency. Furthermore, the lateral electric field intersects the vertical electric field, indicating that the main charge injection point is from the end edge of the gap region close to the word gate.
Positive Bias Temperature Instability (PBTI) Characteristics of Contact-Etch-Stop-Layer-Induced Local-Tensile-Strained HfO(2) nMOSFET
(2008-12-01)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Chiu, Te-Hsin
;
Wang, Jer-Chyi
;
Lai, Chao-Sung
The positive bias temperature instability (PBTI) characteristics of contact-etch-stop-layer (CESL)-strained HfO(2) nMOSFET are thoroughly investigated. For the first time, the effects of CESL on an HfO(2) dielectric are investigated for PBTI characteristics. A roughly 50% reduction Of V(TH) shift can be achieved for the 300-nm CESL HfO(2) nMOSFET after 1000-s PBTI stressing without obvious HfO(2)/Si interface degradation, as demonstrated by the negligible charge pumping current increase (< 4%). In addition, the HfO(2) film of CESL devices has a deeper trapping level (0.83 eV), indicating that most of the shallow traps (0.75 eV) in as-deposited HfO(2) film can be eliminated for CESL devices.
Positive Bias Temperature Instability (PBTI) Characteristics of Contact-Etch-Stop-Layer-Induced Local-Tensile-Strained HfO2 nMOSFET
(2008-12-01)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Chiu, Te-Hsin
;
Wang, Jer-Chyi
;
Lai, Chao-Sung
The positive bias temperature instability (PBTI) characteristics of contact-etch-stop-layer (CESL)-strained HfO2 nMOSFET are thoroughly investigated. For the first time, the effects of CESL on an HfO2 dielectric are investigated for PBTI characteristics. A roughly 50% reduction Of V-TH shift can be achieved for the 300-nm CESL HfO2 nMOSFET after 1000-s PBTI stressing without obvious HfO2/Si interface degradation, as demonstrated by the negligible charge pumping current increase (< 4%). In addition, the HfO2 film of CESL devices has a deeper trapping level (0.83 eV), indicating that most of the shallow traps (0.75 eV) in as-deposited HfO2 film can be eliminated for CESL devices.
The polarity dependence of ONO thickness for wrapped-select-gate (WSG) SONOS memory
(2008)
Wang, Kuan-Ti
;
Chao, Tien-Sheng
;
Wu, Woei-Cherng
;
Lai, Chao-Sung
;
電子物理學系
2-bits/cell operation characteristics of WSG-SONOS memory has been fully studied in different ONO thickness. The 2-bits/cell characteristics of WSG-SONOS memory will be determined by tunneling oxide and total ONO thicknesses. Besides, thicker top oxide thickness will contribute to better gate disturbance performance while maintaining the same drain disturbance. We also found that the excellent endurance can be performed for the device with thinner tunneling oxide thickness. Optimized ONO thickness for WSG-SONOS memory will be demonstrated in this paper.
X-ray photoelectron spectroscopy energy band alignment of spin-on CoTiO(3) high-k dielectric prepared by sol-gel spin coating method
(2008-09-01)
Kao, Kuo-Hsing
;
Chuang, Shiow-Huey
;
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Chen, Jian-Hao
The characteristics of CoTiO(3) high-k dielectric prepared by sol-gel spin coating method had been demonstrated. High electrical permittivity (k similar to 40.2) of CoTiO(3) dielectric was extracted via the transmission electron microscopy image and capacitance-voltage curves. In addition, the valence band offset between thermal SiO(2) and spin-on CoTiO(3) was about 4.0 eV, which was detected by x-ray photoelectron spectroscopy. The band gaps of thermal SiO(2) and spin-on CoTiO(3) were 9.0 and 2.2 eV, respectively. Energy band alignment of spin-on CoTiO(3) directly with SiO(2) and indirectly with Si was determined in this work. (c) 2008 American Institute of Physics.
X-ray photoelectron spectroscopy energy band alignment of spin-on CoTiO3 high-k dielectric prepared by sol-gel spin coating method
(2008-09-01)
Kao, Kuo-Hsing
;
Chuang, Shiow-Huey
;
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Chen, Jian-Hao
The characteristics of CoTiO3 high-k dielectric prepared by sol-gel spin coating method had been demonstrated. High electrical permittivity (k similar to 40.2) of CoTiO3 dielectric was extracted via the transmission electron microscopy image and capacitance-voltage curves. In addition, the valence band offset between thermal SiO2 and spin-on CoTiO3 was about 4.0 eV, which was detected by x-ray photoelectron spectroscopy. The band gaps of thermal SiO2 and spin-on CoTiO3 were 9.0 and 2.2 eV, respectively. Energy band alignment of spin-on CoTiO3 directly with SiO2 and indirectly with Si was determined in this work. (c) 2008 American Institute of Physics.