Browsing by Author "Wu, Ya-Ping"

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A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
(2015-05-01)
Lu, Chien-Yu
;
Chuang, Ching-Te
;
Jou, Shyh-Jye
;
Tu, Ming-Hsien
;
Wu, Ya-Ping
This brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write bitline (WBL) and cross-point data-aware write structure to facilitate robust subthreshold operation and bit-interleaving architecture for enhanced soft error immunity. The design employs a variation-tolerant line-up write-assist scheme where the timing of area-efficient boosted write wordline and negative WBL are aligned and triggered/initiated by the same low-going global WBL to maximize the write-ability enhancement. A 72-kb test chip is implemented in United Microelectronics Corp. 40-nm low-power (40LP) CMOS. Full functionality is achieved for V-DD ranging from 1.5 to 0.32 V without redundancy. The measured maximum operation frequency is 260 MHz (450 kHz) at 1.1 V (0.32 V) and 25 degrees C. At 0.325 V and 25 degrees C, the chip operates at 600 kHz with 5.78 mu W total power and 4.69 mu W leakage power, offering 2x frequency improvement compared with 300 kHz of our previous 72-kb 9T subthreshold SRAM design in the same 40LP technology. The energy efficiency (power/frequency/IO) at 0.325 V and 25 degrees C is 0.267 pJ/bit, a 23.7% improvement over the 0.350 pJ/bit of our previous design.
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
(2012-12-01)
Lu, Chien-Yu
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Tu, Ming-Hsien
;
Yang, Hao-I
;
Wu, Ya-Ping
;
Huang, Huan-Shun
This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bit-line (RPBL) structure and negative bit-line (NBL) write-assist. The RPBL scheme provides over 40% read access performance improvement for VDD below 0.4 V compared with the conventional hierarchical bit-line structure. A variation-tolerant ripple-initiated NBL write-assist scheme with the transient negative pulse coupled only into the single selected local bit-line segment is employed to enhance the NBL, boosting efficiency and reducing power consumption. The 331 x 385 mu m(2) 72-Kb SRAM macro has been fabricated in UMC 40-nm low-power CMOS technology and was tested with full suites of SRAM compiler qualification patterns. Error-free full functionality without redundancy is achieved from 1.5 V down to 0.33 V. The measured maximum operation frequency is 220 MHz (500 kHz) at 1.1 V (0.33 V) and 25 degrees C. The measured total power consumption is 3.94 mu W at 0.33 V, 500 kHz, and 25 degrees C.
A High-Performance Low V(MIN) 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control
(2011)
Yang, Hao-I
;
Yang, Shih-Chi
;
Hsia, Mao-Chih
;
Lin, Yung-Wei
;
Lin, Yi-Wei
This paper describes a high-performance low V(MIN) SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bit-interleaving architecture and achieving low V(MIN). A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943MHz at 1.2V VDD and 209MHz at 0.6V VDD.
High-Performance 0.6V V-MIN 55nm 1.0Mb 6T SRAM with Adaptive BL Bleeder
(2012)
Yang, Hao-I
;
Lin, Yi-Wei
;
Hsia, Mao-Chih
;
Lin, Geng-Cing
;
Chang, Chi-Shin
This paper presents a 1.0Mb high-performance 0.6V V-MIN 6T SRAM design implemented in UMC 55nm Standard Performance (SP) CMOS technology. This design utilizes an adaptive LBL bleeder technique to reduce Read disturb and Half-Select disturb of 6T cells while maintaining adequate sensing margin. A bleeder timing control circuit adaptively adjusts the LBL voltage level prior to Read/Write operation to facilitate wide operation voltage range. Hierarchical WL, hierarchical BL, and distributed replica timing control scheme are used to improve SRAM performance. Based on measurement results, the SRAM operates from 1.5V down to 0.6V. The maximum operating frequency is 1.517GHz@1.5V and 469MHz@0.7V.