Browsing by Author "Wu, Yan-Shiun"

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DATC RDF: Robust Design Flow Database
(2017-01-01)
Jung, Jinwook
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Lee, Pei-Yu
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Wu, Yan-Shiun
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Darav, Nima Karimpour
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Jiang, Iris Hui-Ru
In this paper, we present DATC Robust Design Flow Database covering the stages from logic synthesis to physical design [1]. Based on this database, design flow and cross-stage optimization research can be conducted via various EDA tools developed from academia.
MapReduce-Based Pattern Classification for Design Space Analysis
(2018-01-01)
Wu, Yan-Shiun
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Su, Hong-Yan
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Chang, Yi-Hsiang
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Topaloglu, Rasit Onur
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Li, Yih-Lang
With the ongoing reduction of feature size, design for manufacturability is a critical concern in advanced technology nodes. Pattern classification is a promising and widely employed approach for design space analysis, design rule generation, and yield optimization. In this paper, we propose a hybrid algorithm that account for two variations for classification metrics: feature edge displacement and total feature area difference. A MapReduce-based framework is proposed to reduce the complexity of the pattern classification problem such that orders of magnitude of performance improvement can be realized. Our experimental results indicate that regarding accuracy and runtime, this work outperforms the winner of the CAD Contest at ICCAD 2016 in terms of contest scoring measure.
Pin Accessibility Evaluating Model for Improving Routability of VLSI Designs
(2017-01-01)
Su, Hong-Yan
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Nishizawa, Shinichi
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Wu, Yan-Shiun
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Shiomi, Jun
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Li, Yih-Lang
Pin accessibility influences the routability of a design at the stage of block/chip assembling. The estimation model for pin accessibility in previous researches counts the total number of intersections between each pin and M2 routing tracks. It does not consider the variation of pin accessibility as the spacing between a pin and its neighboring pins and metal wires changes. Besides, it cannot properly deal with the off-grid pin access neither. In this paper, we propose a general model for pin accessibility estimation. In the model, all directions to connect to the boundary of a pin are under estimation. Off-grid pin access is also available. Experimental results show that the reduction rate of minimum area to complete the routing of a circuit can be 7.0% on average. Due to the diminishment of required area for routing, the total number of vias for higher metal layer also decrease under the same area constraint.