Browsing by Author "YAN, JT"

Now showing 1 - 15 of 15

A FUZZY CLUSTERING-ALGORITHM FOR GRAPH BISECTION
(1994-12-09)
YAN, JT
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HSIAO, PY
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交大名義發表
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資訊工程學系
;
National Chiao Tung University
A fuzzy clustering algorithm based on global connection information is proposed to solve the graph bisection problem.
A GENERAL SWITCHBOX ROUTER WITH VIA MINIMIZATION
(1993)
YAN, JT
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HSIAO, PY
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資訊工程學系
;
Department of Computer Science
A PARTITIONING-BASED APPROACH FOR THE ORIENTATION AND ROTATION ASSIGNMENTS OF MACRO CELLS
(1994)
YAN, JT
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HSIAO, PY
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資訊工程學系
;
Department of Computer Science
A ROBUST OVER-THE-CELL CHANNEL ROUTER
(1993-10-01)
CHANG, LD
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HSIAO, PY
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YAN, JT
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SHEW, PW
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資訊工程學系
In this paper, we present an efficient algorithm for over-the-cell routing in the standard cell layout design technology. Two variations are discussed: one aims to minimize the channel density with fewest tracks over the cells while the other aims to minimize the final channel width. Our algorithm can fit both the two-layer and three-layer routing models. With the two-layer model, there is a single routing layer over the cells for intercell connections. While with the three-layer model, there are two disjoint routing layers over the cells for intercell connections. In our approach, we decompose the problem into two phases: (1) over-the-cell routing and (2) conventional channel routing. The over-the-cell routing phase, which is executed iteratively, consists of two steps, routing over the cells and choosing net segments within the channel. For each iteration in the over-the-cell routing phase, our algorithm removes a net or a subnet which intersects the column with highest column density and route it over the cells according to some prioritized criteria. In comparison with the previous researches, our approach achieved the best effectiveness and has used the least CPU-time. On the average, the execution speed of our router is 163 and 4163 times faster than that of [8] and [9], respectively. Besides, our algorithm can produce results comparable to those produced by the WISER algorithm [10].
AN EFFICIENT HEURISTIC APPROACH ON MINIMIZING THE NUMBER OF FEEDTHROUGH CELLS IN STANDARD CELL PLACEMENT
(1995)
YAN, JT
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資訊工程學系
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Department of Computer Science
AN OPTIMAL ALGORITHM ON MINIMUM RECTANGULAR PARTITION OF VLSI LAYOUT
(1993)
YAN, JT
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HSIAO, PY
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資訊工程學系
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Department of Computer Science
AREA-RATIO-CONSTRAINED MIN-CUT PARTITIONING FOR ROW-BASED PLACEMENT
(1994)
YAN, JT
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資訊工程學系
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Department of Computer Science
CONVERGE - A CIRCULAR-ASSIGNMENT-BASED SWITCHBOX ROUTER WITH VIA REDUCTION
(1995-01-01)
YAN, JT
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HSAIO, PY
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交大名義發表
;
資訊工程學系
;
National Chiao Tung University
The authors propose a new circular-assignment-based switchbox router, CONVERGE, based on segment assignment in circular routing. The CONVERGE router is divided into three phases: the iterative phase, the merging phase and the via reduction phase. In the iterative phase, circular routing will be applied to assign vertical or horizontal segments cycle by cycle. In the merging phase, if switchbox routing is successful, the routing result can be further improved by merging adjacent segments of the same routing net. Finally, in the via reduction phase, constrained layer assignment can further reduce the number of vias. As a result, many benchmarks have been tested on the switchbox router, and these benchmarks are successfully routed. In addition, the proposed switchbox router has better routing results than other switchbox routers on vias and wire length.
DESIGNING A COMPLEMENTARY DESIGN RULE CHECKER BASED ON A BINARY BALANCED QUAD LIST QUAD TREE
(1992-07-01)
HSIAO, PY
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YAN, JT
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交大名義發表
;
資訊工程學系
;
National Chiao Tung University
An efficient real time VLSI-CAD tool, the complementary design rule checker (CDRC), composed of one interactive phase and one batch phase is presented. It is a general geometrical design rule model which checks some of the layout constraints in the interative phase and the other constraints in the batch phase. Those classified constraints are disjointed, and each one of them should be checked only once either during the interactive or batch phase. This system and the embedded layout editor are designed on the basis of the binary balanced quad list quad tree (BBQLQT) and its region query functions. The BBQLQT is more efficient than the most recently published spatial data structure, the Weyten's quad list quad tree. One day, provided that the BBQLQT has being further improved, the performance of our system will be promoted without giving more additional design effort. This system is therefore proven to be fully modularised and independent of any of the other spatial data structures.
FUZZY-CLUSTERING-BASED ALGORITHM FOR CIRCUIT PARTITIONING IN STANDARD CELL PLACEMENT
(1995-02-02)
YAN, JT
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交大名義發表
;
資訊工程學系
;
National Chiao Tung University
;
Department of Computer Science
The technique of circuit partitioning has been applied to standard cell placement for many years. A fuzzy-clustering-based algorithm is proposed to obtain a better two-way area-constrained partitioning for a partitioning-oriented standard cell placement. The proposed algorithm has tested several industrial circuit benchmarks, and the experimental results have shown that the algorithm obtains a better partitioning than the traditional F-M algorithm.
ORIENTATION ASSIGNMENT OF STANDARD CELLS USING A FUZZY MATHEMATICAL TRANSFORMATION
(1994)
YAN, JT
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HSIAO, PY
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資訊工程學系
;
Department of Computer Science
ORIENTATION ASSIGNMENT OF STANDARD CELLS USING A FUZZY MATHEMATICAL TRANSFORMATION
(1995-03-01)
YAN, JT
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HSIAO, PY
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資訊工程學系
;
Department of Computer Science
It is well known that minimising total wire length reduces routing area in a standard cell layout. After the placement phase, another advanced improvement on total wire length is made by assigning the orientations of standard cells. In the paper, based on fuzzy c-means clustering, the authors develop two-way constrained fuzzy graph clustering and the transformation between the orientation assignment of standard cells and the constrained graph bisection to minimise total wire length. Finally, the proposed algorithm has tested several standard cell layouts, and the experimental results show that the proposed algorithm produces significant wire reduction on total wire length.
REGION DEFINITION FOR MINIMIZING THE NUMBER OF SWITCHBOXES AND ORDERING ASSIGNMENT
(1994)
YAN, JT
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HSIAO, PY
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資訊工程學系
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Department of Computer Science
THE MODULE ORIENTATION PROBLEM-BASED ON MANHATTAN WIRE MEASURE IS STILL NP-COMPLETE
(1993)
YAN, JT
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HSIAO, PY
;
資訊工程學系
;
Department of Computer Science
Two-way balance-tolerant partitioning based on fuzzy graph clustering for hierarchical design of VLSI systems
(1995)
YAN, JT
;
資訊工程學系
;
Department of Computer Science