Browsing by Author "YANG, RY"

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HIGH-THROUGHPUT DATA COMPRESSOR DESIGNS USING CONTENT ADDRESSABLE MEMORY
(1994)
YANG, RY
;
LEE, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
HIGH-THROUGHPUT DATA COMPRESSOR DESIGNS USING CONTENT-ADDRESSABLE MEMORY
(1995-02-01)
LEE, CY
;
YANG, RY
;
交大名義發表
;
電子工程學系及電子研究所
;
National Chiao Tung University
The paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well known LZ77 algorithm, The architecture mainly consists of three units, namely, content addressable memory, match-logic unit, and output-stage unit, The content-address-memory unit generates a Set of hits signals which identify those positions whose symbols in a specified window are the same as the input symbol. These hits signals are then passed to the match-logic unit which determines both match length and location to form the kernel of compressed data, These two items are then passed to the output-stage unit for packetisation before being sent out. Simulation results show that, based on a 0.8 mu m CMOS process technology, a clock speed of up to 50 MHz can be achieved for a VLSI design containing a 2K buffer size. This implies that the developing data compressor chip can handle many real-life applications, such as in high-speed data storage and networking systems,