Browsing by Author "YANG, WW"

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A PARALLEL BIT-LEVEL MAXIMUM MINIMUM SELECTOR TO DIGITAL AND VIDEO SIGNAL-PROCESSING
(1994-10-01)
LEE, CY
;
JUAN, SC
;
YANG, WW
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a novel circuit for parallel bit-level maximum/minimum selection. The selection is based on a label-updating scheme which sequentially scans a set of data patterns from MSB to LSB and generates corresponding labels. The complete circuit realizing this scheme consists of a set of updating units and a global OR unit, where each updating unit is composed of only a few basic gates. Due to structure modularity, the developed circuit provides a very cost-effective hardware solution for comparing large volumes of data patterns as those required in digital and video signal processing.
DESIGN OF A FAST SEQUENTIAL DECODING ALGORITHM BASED ON DYNAMIC SEARCHING STRATEGY
(1994)
YANG, WW
;
JENG, LF
;
LEE, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
FAST SEQUENTIAL-DECODING ALGORITHM-BASED ON DYNAMIC SEARCHING STRATEGY
(1994-10-01)
LEE, CY
;
YANG, WW
;
JENG, LF
;
交大名義發表
;
電子工程學系及電子研究所
The authors present a new sequential decoding algorithm based on dynamic searching strategy to improve decoding efficiency. The searching strategy is to exploit both 'sorting' and 'path recording' techniques. By means of sorting, it is possible to identify the correct path in a very fast way and then, by the recording, the bit sequence can be recovered without degrading decoding performance. The authors also develop a conditional resetting scheme to overcome the buffer overflow problem encountered in conventional sequential decoding algorithms. Simulation results show that, for a given code, the decoding efficiency remains the same as that obtained from maximum likelihood function by appropriately selecting sorting length and decoding depth. In addition, this algorithm can easily be mapped onto an area-efficient VLSI architecture to implement long constraint length convolutional decoders for high-speed digital communications.