Browsing by Author "Yan, Jin-Tai"

Now showing 1 - 6 of 6

Block-Level Thermal Model for Floorplan Stage in VLSI Design Flow
(2008)
Lin, Shun-Hua
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Yan, Jin-Tai
;
Chiueh, Herming
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電信工程研究所
;
Institute of Communications Engineering
Thermal issues have become a determinant factor to result in very large scale integrated (VGSI) circuits work or malfunction. For this reason, the paper proposed an efficient block-level thermal model for temperature calculation in the floorplan stage among the integrated circuit (IC) design flow. Furthermore, the model accurately profiles the temperature difference between all thermal blocks and overcomes the very long computational time issue existing in traditional tile-based thermal model. We not only prove the timing complexity by theory but also use five floorplan benchmarks to test our model. Observing the experimental results, the temperature calculation times for all benchmarks are really direct ratio of total amount of blocks. Hence our block-level thermal model really can reduce the temperature calculating time and provide useful temperature differences for rearranging the floorplan.
Construction of Delay-Driven GNR Routing Tree
(2019-01-01)
Yan, Jin-Tai
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Yen, Chia-Heng
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生物資訊及系統生物研究所
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Institude of Bioinformatics and Systems Biology
It is known that graphene nanoribbon (GNR) based devices and interconnects can be treated to be better alternative in nano-scale designs. In this paper, given a source pin and a set of target pins inside a GNR grid-based routing plane, based on the consideration of the wirelength and bending delay in graphene nanoribbon, an efficient routing algorithm can be proposed to construct a delay-driven GNR routing tree with minimizing the total wirelength for the target pins. Compared with Das's algorithm [9] on total wirelength and maximum source-to-target delay, the experimental results show that our proposed routing algorithm only uses 8.05% of the extra wirelength to reduce 23.13% of the maximum delay in the construction of a delay-driven GNR routing tree for 6 tested examples on the average.
Feasible Assignment of Micro-Bumps in 3D ICs
(2018-01-01)
Yan, Jin-Tai
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Yen, Chia-Heng
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生物資訊及系統生物研究所
;
Institude of Bioinformatics and Systems Biology
For the signal connections between two adjacent dies in 3D ICs, the redistributed layers (RDLs) routing from 10 pads to micro-humps plays an important role. In this paper, given a set of nets on the upper and lower RDLs between two adjacent dies, based on the separation of one 2-pin net on the upper and lower RDLs using one micro-hump, an efficient two-phase algorithm can he proposed to assign feasible micro bumps onto the nets to minimize the overlapping degree and the X-type intersections on the routing regions for single-layer RDI, routing. Compared with Kuan's algorithm and Yan's algorithm in the micro-hump assignment for single-layer RBI, routing, the experimental results show that our proposed algorithm can use less CPU time to assign feasible micro humps onto the given nets and obtain 100% routability with shorter wirelength in 5 tested examples.
Floorplan-aware decoupling capacitance budgeting on equivalent circuit model
(2006)
Yan, Jin-Tai
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Lin, Kai-Ping
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Luo, Yue-Fong
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資訊工程學系
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Department of Computer Science
In this paper, based on an equi valent circuit model for any noise-aware power network an accurate estimation uses an exponential discharge style in the equivalent RC circuit to predict the decoupling capacitance(decap) size of any circuit module in a given floorplan. Furthermore, a floorplan-aware budgeting approach is proposed to assign feasible decaps onto all the circuit modules to release all the IR-drop noises in the floorplan. The experimental results show that our proposed budgeting approach based on an accurate estimation obtains very promising results for MCNC benchmark circuits.
Optimal shielding insertion for inductive noise avoidance
(2006)
Yan, Jin-Tai
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Lin, Kuen-Ming
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Chen, Yen-Hsiang
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資訊工程學系
;
Department of Computer Science
In this paper, given a set of parallel wires between a pair of adjacent PIG lines, according to the definition and computation of the inductive noise and the classification of violation wires, an O(n) optimal approach is proposed to insert shields into these parallel wires for the avoidance of inductive noise, where n is the number of a set of given parallel wires. The experimental results show that our proposed approach can use less CPU time to minimize the number of inserted shields for the avoidance of inductive noise.
Timing-Constrained Yield-Driven Redundant Via Insertion
(2008)
Yan, Jin-Tai
;
Chen, Zhi-Wei
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Chiang, Bo-Yi
;
Lee, Yu-Min
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電信工程研究所
In this paper, based on the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias. For the Poisson yield model in redundant via insertion, the experimental results show that our proposed enhanced two-phase insertion approach can further reduce 0.006% total wire length on the average with the reduction of 0.0002% chip yield to maintain 100% timing constraints for the tested benchmarks.