Browsing by Author "Yan, Tzu-Chao"

Now showing 1 - 16 of 16

A 0.75-2.67 GHz 5-bit Vector-Sum Phase Shifter
(2013)
Yan, Tzu-Chao
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Lin, Wei-Zhen
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Kuo, Chien-Nan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 5-bit active vector-sum phase shifter operated in 0.75-2.67 GHz is implemented in 0.18-mu m CMOS technology. A tunable RC quadrature all-pass filter and a resistor-string VGA are proposed for quadrature phase generation and magnitude ratio tuning, respectively. The chip size is 0.89 mm(2). The DC power consumption of core circuit is 6.39 mW from 1.8 V supply. The RMS magnitude error and RMS phase error are below 0.74 dB and 7.2 degrees.
A 1-4 GHz Frequency-to-Voltage Converter Design
(2012)
Kuan, Chih-Kuang
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Yan, Tzu-Chao
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Kuo, Chien-Nan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A broadband frequency-to-voltage converter is designed to operate at the multi-GHz frequency band. The circuit detects the input signal frequency and generates a DC output voltage correspondingly, regardless of the input power variation through a two-path signal process of frequency discrimination and signal power reference. One advantage of the design utilizing power detection makes the method feasible for very high frequency applications. The integrated design is verified in an integrated system mixed with off-the-shelf commercial components. Measurement results show a maximum output voltage RMS error of 2.1% over the input frequency from 1 GHz to 4 GHz with the input power level -30 dBm to 0 dBm.
A 1-5 GHz Frequency-to-Voltage Converter Using Limiting Amplifier
(2016)
Lin, Han-Bo
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Yan, Tzu-Chao
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Kuo, Chien-Nan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A frequency-to-voltage converter (FVC) is designed for directly converting an input radio-frequency to a dc output voltage over a wide microwave frequency range. The proposed circuit consists of a limiting amplifier (LA) for converting input frequency to correspond ac magnitude and a power detector for ac magnitude to dc voltage conversion. Consequently, the circuit converts the signal frequency of 1-5 GHz to the measured dc voltage of 0.25-1.39 V under the input power level at +5 dBm. The RMS error is below 1.37 %. Implemented in 0.18 mu m CMOS technology, the dc power consumption varies from 17.4 to 19.4 mW with 1.8 V supply voltage, depending on the input frequency. The fabricated chip occupies the size of 860 x 500 mu m(2).
A 1.3 GHz-5.3 GHz Wideband, High Linearity Balun Low Noise Amplifier
(2011)
Yang, Kai-Hsiang
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Kuo, Ming-Ching
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Yan, Tzu-Chao
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Kuo, Chien-Nan
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電子工程學系及電子研究所
In this work, a balun low-noise amplifier (LNA) is designed and implemented in 0.18-mu m CMOS process. The bulk cross-coupling (BCC) and capacitance cross-coupling (CCC) techniques are introduced in this LNA, which not only increase gain and linearity but also decrease noise figure. The 3 dB bandwidth extends from 1.27 GHz to 5.31 GHz. The maximum differential gain is 10.13 dB. Measured at 3 GHz, P-1dB and IIP3 are -10 dBm and 0 dBm, respectively. The LNA core circuit dissipates 7.32 mW from 1.8 V power supply.
A 60 GHz Injection-Locked Frequency Tripler With Spur Suppression
(2010-10-01)
Kuo, Chien-Nan
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Yan, Tzu-Chao
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 60 GHz injection-locked frequency tripler is designed to improve spectral purity with spur suppression of the fundamental and the even-order harmonics. Several circuit designs are utilized in the harmonic current injection circuit to maximize the third-order harmonic and minimize the undesired harmonic current outputs, including notch filters and a capacitive cross-coupled transistor pair. With the input signal of 0.5 dBm at 19.7 GHz, the harmonic rejection ratios of the fundamental, and the second-order achieve 31.3 dBc, and 45.8 dBc, respectively. Implemented in 0.13 mu m CMOS technology, the core circuit consumes power of 9.96 mW with 1.2 V supply voltage. The entire die occupies an area of 985 x 866 mu m(2)
A CMOS Up-Conversion Mixer with Wide IF Bandwidth for 60-GHz Applications
(2009)
Chen, Min-Chiao
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Chen, Huan-Sheng
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Yan, Tzu-Chao
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Kuo, Chien-Nan
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交大名義發表
In this paper, a direct up-conversion mixer with wide intermediate frequency (IF) bandwidth is designed and fabricated for 60-GHz applications. The up-converted differential signal is transformed to single-ended signal through an on-chip balun. In addition, an injection-locked frequency tripler is integrated for local oscillator signal generation. The measured results shows the maximum conversion gain of -5.6 dB, the input-referred JAB compression point (IP1dB) of -14 dBm, the third-order intercept point (IIP3) of -4 dBm, and 3-dB IF bandwidth of 3.5 GHz. The proposed up-conversion mixer is fabricated using 0.13-mu m standard CMOS technology, and it draws only 2.25 mA from 1.2-V supply.
A K-Band CMOS Quadrature Frequency Tripler Using Sub-Harmonic Mixer
(2009-12-01)
Kuo, Chien-Nan
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Chen, Huan-Sheng
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Yan, Tzu-Chao
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A low-power frequency tripler is designed by using the sub-harmonic mixer configuration for K-band applications. The proposed circuit features quadrature signal generation, applicable to LO signal synthesis in millimeter-wave wireless transceivers. It achieves conversion gain of -5.7 dB at the output frequency of 21 GHz. Implemented in a 0.18 mu m CMOS technology, the circuit consumes power of 7.5 mW with 1.5 V supply voltage. The entire die occupies an area of 1000 x 1050 mu m(2).
A Low-Cost Broadband Bondwire Interconnect for THz Heterogeneous System Integration
(2015)
Li, Chun-Hsing
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Lai, Chih-Wei
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Yan, Tzu-Chao
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Kuo, Chien-Nan
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電機工程學系
A low-cost broadband bondwire interconnect is proposed for THz heterogeneous system integration. A transversal path composed of two transmission lines and a bondwire is introduced to effectively reduce the bondwire effect of an original signal path consisted of a single bondwire only. Simulation results indicate that the return loss and insertion loss can be better than 15 dB and 2.3 dB from dc to 456 GHz, respectively. Measured interconnect loss is around 0 dB to 1.5 dB from 320 to 340 GHz.
A Q-band Direct Divide-by-4 Injection-Locked Frequency Divider with Quadrature Outputs
(2010-01-01)
Yan, Tzu-Chao
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Shih, Horng-Yuan
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Yang, Tzu-Yi
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Kuo, Chien-Nan
;
交大名義發表
A divide-by-4 injection-locked frequency divider is designed for applications in the millimeter-wave frequency range. The proposed circuit also features in quadrature phase outputs by using a quadrature voltage-controlled oscillator. The input signal is injected into the common-mode node at the tail current source directly. Implemented in a 0.13 mu m CMOS technology, the core circuit consumes dc power of 3.66mW with 1.2 V supply voltage. The operation range achieves 1.95 GHz. The entire die occupies an area of 974x726 um(2).
An Inductorless RC-based Quadrature Phase Generator and Its Application to Vector-Sum Phase Shifter
(2014-01-01)
Yan, Tzu-Chao
;
Lin, Wei-Zhen
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Kuo, Chien-Nan
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An inductorless quadrature phase generator is designed and implemented in 0.18 mu m CMOS technology. The proposed circuit is composed of two resistors, two capacitors, and four differential amplifiers. The performance of proposed circuit is verified by a single sideband (SSB) mixer and a vector-sum phase shifter. Measurement results show that the image rejection ratio is 42.38 dBc at 2.16 GHz. The measured RMS phase error and RMS magnitude error are below 3.5 degrees and 0.55 dB in 2-2.6 GHz, respectively.
An Ultra-Low Power Interface CMOS IC Design for Biosensor Applications
(2012)
Hu, Weibo
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Liu, Yen-Ting
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Das, Vighnesh
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Schecht, Cliff
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Tam Nguyen
This paper presents a design example of an ultra-low power single-channel analog front-end (AFE) integrated circuits (IC) and system for biomedical sensing applications. The 0.18-mu m CMOS AFE IC design includes a low noise instrumentation amplifier (INA), a low-pass filter (LPF), a variable gain amplifier (VGA), and a successive approximation register (SAR) analog-to-digital converter (ADC). The AFE IC architecture is analyzed on the system level to minimize total power consumption with high integration and optimized for an ECG sensing system. SPICE simulations of the AFE IC channel validate the ultra-low power IC design methodology for heartbeat detection with less than 1 mu A/channel.
CMOS THz Transmissive Imaging System
(2014)
Yan, Tzu-Chao
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Li, Chun-Hsing
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Lai, Chih-Wei
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Chen, Wei-Cheng
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Chao, Tzu-Yuan
This paper presents a THz imaging system composed of a signal source and a signal sensor in CMOS technology The signal source integrates a 338 GHz oscillator in 40-nm CMOS and an antenna array on a Benzocyclobutene (BCB) carrier using the SoP (System-on-Package) technique. The measured EIRP achieves +8 dBm. The signal sensor is implemented in 0.18 mu m CMOS. The measured maximum responsivity is 632 kV/W at 332 GHz. The signal source and signal sensor consume dc power of 37.5 mW and 7.92 mW, respectively. The resolution of the proposed THz imaging system is 4 mm.
Electronic THz Transmissive Imaging System
(2015)
Chen, Wei-Cheng
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Lai, Chih-Wei
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Yan, Tzu-Chao
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Li, Chun-Hsing
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Chao, Tzu-Yuan
An electronic THz transmissive imaging system is presented in this work. This system is composed of a CMOS signal source, a CMOS signal sensor, lenses, and commercial electronic chopping components. The output frequency of the signal source is 339 GHz, and the responsivity of the signal sensor is 200 kV/W. The total dc power consumption of those CMOS circuits is 91.02 mW. Using electronic chopping at the frequency up to 100 kHz helps improve the system dynamic range and makes imaging feasible. The resolution of the realized imaging system achieves 2 mm.
Low-Cost High-Performance CMOS Terahertz Imaging System
(2015)
Li, Chung Hsing
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Yan, Tzu-Chao
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Chang, Yuhsin
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Chen, Chyong
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Kuo, Chien-Nan
CMOS technology has found its way in THz imaging applications. Utilizing the plasma wave theory, a MOSFET device can detect THz radiation beyond the cutoff frequency. Assisted by the system-on-packaging technique, a CMOS source delivers radiation power more effectively. An imaging system demonstrates that a low-cost CMOS solution is feasible.
The Experimental Study of THz Image Sensor in 0.18 mu m CMOS Technology
(2014)
Lai, Chih-Wei
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Chen, Wei-Cheng
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Yan, Tzu-Chao
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Li, Chun-Hsing
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Kuo, Chien-Nan
In this study, four different types of power detectors are implemented in 0.18 mu m CMOS technology for the THz image sensor application. These power detectors include common-source with and without supply voltage, and common gate with and without supply voltage. The measured responsivities at 332 GHz are 632 kV/W, 13.2 kV/W, 16.2 kV/W, and 9.1 kV/W, respectively. The image resolution of the proposed THz sensor is 2 mm.
Wideband Time-Delay Circuit
(2011-01-01)
Chang, Yao-Wei
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Yan, Tzu-Chao
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Kuo, Chien-Nan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Limitations of the delay bandwidth in active delay circuits can be significantly improved in high-order transfer functions. In this paper, a flat wideband delay circuit is presented using the 2nd-order form of the Pade approximant. The delay circuit is designed and implemented in 0.18 mu m CMOS technology. The measured results show that the circuit achieves a delay time of 49 psec in the GHz frequency range. The power consumption of the core circuit is 7.88 mW from 1.8 V supply voltage. The entire die occupies an area of 520x820 mu m(2)