Browsing by Author "Yang, C. W."

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A New Variation Plot to Examine the Interfacial-dipole Induced Work-function Variation in Advanced High-k Metal-gate CMOS Devices
(2016)
Hsieh, E. R.
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Wang, Y. D.
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Chung, Steve S.
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Ke, J. C.
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Yang, C. W.
The interfacial dipole and bulk trap in HKMG stack have been found to be significant to the work function variation (sigma V-WF), in addition to the metal grains. In order to differentiate their effects on sigma V-WF, a new variation plot is proposed and the dipole and trap effects can be distinguished. Here, we propose a simple experimental method to separate the effects of MG/HK and HK/IL interfacial dipoles. In pMOSFET, HK/IL dipoles dominate HK induced variation; MG/HK dipoles are dominant in nMOSFET. However, in terms of the reliability test, after PBTI stress, HK bulk traps play a major role in the variation of nMOSFET, while after NBTI, HK/IL dipoles are strengthened by hydrogen bonds and still dominant in work function variation of pMOSFET. Design guideline is provided to deal with the passivation of high-k traps by nitrogen concentration and the improvement of variability in HKMG CMOS devices.
The Demonstration of Low-cost and Logic Process Fully-Compatible OTP Memory on Advanced HKMG CMOS with a Newly found Dielectric Fuse Breakdown
(2015)
Hsieh, E. R.
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Huang, Z. H.
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Chung, Steve S.
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Ke, J. C.
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Yang, C. W.
For the first time, the dielectric fuse breakdown has been observed in HKMG and poly-Si CMOS devices. It was found that, different from the conventional anti-fuse dielectric breakdown, such as the hard and soft breakdowns, this new fuse-breakdown behavior exhibits a typical property of an open gate and can be operated in much lower programming current (<50 mu A), fast speed (similar to 20 mu sec), and excellent data retention, in comparison to the other fuse mechanisms. Based on this new mechanism, we have designed a smallest memory cell array which can be easily integrated into state-of-the-art advanced CMOS technology to realize highly reliable, secure, and dense OTP functionality with very low cost to meet the requirements of memory applications in the IoT era.
The Experimental Demonstration of the BTI-Induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS Devices
(2014)
Hsieh, E. R.
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Lu, P. Y.
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Chung, Steve S.
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Chang, K. Y.
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Liu, C. H.
For the first time, the breakdown path induced by BTI stress can be traced from the RTN measurement. It was demonstrated on advanced high-k metal gate CMOS devices. RTN traps in the dielectric layers can be labeled as a pointer to trace the breakdown path. It was found that breakdown path tends to grow from the interface of HK/IL or IL/Si which is the most defective region. Two types of breakdown paths are revealed. The soft-breakdown path is in a shape like spindle, while the hard breakdown is like a snake-walking path. These two breakdown paths are reflected in a two slopes TDDB lifetime plot. These new findings on the breakdown-path formation will be helpful to the understanding of the reliability in HK CMOS devices.
The Observation of BTI-induced RTN Traps in Inversion and Accumulation Modes on HfO2 High-k Metal Gate 28nm CMOS Devices
(2014-01-01)
Wu, P. C.
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Hsieh, E. R.
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Lu, P. Y.
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Chung, Steve S.
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Chang, K. Y.
A comprehensive analysis on the BTI induced RTN traps in high-k(HK) CMOS devices have been investigated in inversion (inv.) and accumulation (acc.) modes. The combination of two modes for RTN measurement provides a wide range of energy window in high-k gate dielectric, in which a simple extraction method of RTN analysis has been adopted to analyze the gate dielectric dual-layer of advanced HK devices. The results show that inversion mode measurement can only identify the RTN traps in the channel region, which is related to the V-th degradation. While, accumulation mode may detect the traps inside the gate-drain overlap region which provides better understanding of GIDL current. This basic understanding is of critical important to the quality development of HK gate dielectrics in advanced CMOS technologies.
The RTN Measurement Technique on Leakage Path Finding in Advanced High-k Metal Gate CMOS Devices
(2015)
Hsieh, E. R.
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Lu, P. Y.
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Chung, Steve S.
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Ke, J. C.
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Yang, C. W.
In this paper, the evolution of BTI induced leakage paths has been evaluated by I-g-RTN technique and demonstrated on HK/MG CMOS devices. First, RTN measurement has been elaborated to identify the location of traps and their correlation to the leakage current. Then, the measured gate current transient can he used to analyze the formation of breakdown path. The results show that the evolution of leakage paths can be divided into three stages, i.e., (I) the early stage- only gate leakage and discrete RTN traps are observed, (2) the middle stage- the traps interacting with the percolation paths and exhibits a multi-level current variation, and (3) the last stage- the formation of breakdown path. These findings provide useful information on the understanding of gate dielectric breakdown in high-k CMOS devices.
Twin-GD: A new twin gated-diode measurement for the interface characterization of ultra-thin gate oxide MOSFET's with EOT down to 1nm
(2006)
Lee, G. D.
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Chung, S. S.
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Mao, A. Y.
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Lin, W. M.
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Yang, C. W.
In this paper, a new twin gated-diode (T-GD) method has been greatly improved for the oxide interface characterization of MOS devices with gate oxide as thin as 1nm (EOT). With the scaling of gate oxide thickness into 1mn regime, reported GD measurement can not give correct measurement due to gate tunneling leakage current. Here, we provide a simple method to remove this limitation. This method has been demonstrated successfully for the ultra-thin (EOT = 10.2 angstrom) gate oxide nMOSFET devices. Application of the method to the PBTI effects of high-k gate dielectric devices has been demonstrated. It was found that high-K device has worse gate oxide quality, but its interface damage is less than that of control oxide.