Browsing by Author "Yang, CJ"

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Effect of temperature and illumination on the instability of a-Si : H thin-film transistors under AC gate bias stress
(2001-04-01)
Huang, CY
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Teng, TH
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Yang, CJ
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Tseng, CH
;
Cheng, HC
This work investigates the temperature and illumination effects on the a-SM thin-film transistors (a-SiH TFTs) under AC gate bias stress to find the larger threshold voltage shift and subthreshold swing change for the bias-temperature-stress (BTS) and bias-illumination-stress (BIS). Excess carriers from thermal-generation electron-hole pairs or photoexcited electron-hole pairs may significantly influence the instability of a-SM TFTs during bias stress. The instability mechanisms originate from the carrier-induced defect Creation enhanced by thermal generation in the BTS case and also emphasized by photoexcitation for the BIS case. Both stress conditions will induce a larger threshold voltage shift and higher cutoff frequency than those for simple bias stresses.
Electromigration study in SnAg3.8Cu0.7 solder joints on Ti/Cr-Cu/Cu under-bump metallization
(2003-11-01)
Hsu, YC
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Shao, TL
;
Yang, CJ
;
Chen, C
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材料科學與工程學系
This paper investigates the electromigration-induced failures of SnAg3.8Cu0.7 flip-chip solder joints. An under-bump metallization (UBM) of a Ti/Cr-Cu/Cu trilayer was deposited on the chip side, and a Cu/Ni(P)/Au pad was deposited on the BT board side. Electromigration damages were observed in the bumps under a current density of 2 x 10(4) A/cm(2) and 1 x 10(4) A/cm(2) at 100 degreesC and 150 degreesC. The failures were found to be at the cathode/chip side, and the current crowding effect played an important role in the failures. Copper atoms were found to move in the direction of the electron flow to form intermetallic compounds (IMCs) at the interface of solder and pad metallization as a result of current stressing.
Formation of silicided shallow p(+) n junctions by BF2+ implantation into thin amorphous-Si or Ni/amorphous-Si films on Si substrates and subsequent Ni silicidation
(1999-03-01)
Juang, MH
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Hu, MC
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Yang, CJ
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The process scheme that forms NiSi-silicided shallow p(+)n junctions by BF2+ implantation into thin amorphous-Si (a-Si) or Ni/a-Si films on Si substrates and subsequent Ni silicidation has been studied. As for the scheme using a-Si as an implantation barrier, an NiSi-silicided junction with a leakage of about 0.7 nA/cm(2) at - 5 V is obtained by the sample Ni silicided at 700 degrees C for 30 min. The implantation energy and the crystallinity of the deposited Si films after annealing would greatly affect the junctions formed at various temperatures, attributable to different, implantation effects and boron depth profile. However, the junctions formed by rapid thermal processing or high implant energy are considerably degraded at 800 degrees C, attributable to anomalous Ni penetration into the Si substrate with the further silicidation of NiSi into NiSi2. On the other hand, the specimens with Ni/a-Si as an implantation barrier sustain few defects, thus significantly suppressing the junction degradation at 800 degrees C. However the formed junctions are worse than those by the former scheme, mainly due to lower dopant drive-in efficiency. (C) 1999 American Vacuum Society. [S0734-211X(99)03902-5].
Generalized interconnect delay time and crosstalk models: I. Applications of interconnect optimization design
(2001-12-01)
Lee, TGY
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Tseng, TY
;
Wong, SC
;
Yang, CJ
;
Liang, MS
New analytical models for estimating the delay time of single line and coupled interconnect for ramp input waveform are derived, The accuracy of the signal delay time and crosstalk noise voltage models for various driver resistances, loading capacitances, and input-ramping rates has also been verified by simulation program with integrated circuit emphasis (SPICE) simulation. Based on the delay and crosstalk models, interconnect optimization design can be discussed thoroughly. The proposed guaranteed-performance interconnect design method is also discussed. These models are useful for performance estimation and layout optimization in VLSI synthesis as well as process optimization in technology development.
Generalized interconnect delay time and crosstalk models: II. Crosstalk-induced delay time deterioration and worst crosstalk models
(2001-12-01)
Lee, TGY
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Tseng, TY
;
Wong, SC
;
Yang, CJ
;
Liang, MS
New analytical models for estimating crosstalk-induced delay time deterioration and the worst crosstalk models of a coupled interconnect for ramp input waveform are derived. The accuracy of these compact models at various driver resistances, loading capacitances, and input-ramping rates is verified by simulation program with integrated circuit emphasis (SPICE) simulation for the parallel interconnect system. The effects of crosstalk noise on the delay time at various ramp input rise times, for both simultaneous and non-simultaneous switching cases, are discussed here. In this study we show that crosstalk noise will be a limiting factor for future fast transition signals. The results reported herein are useful in the studies of delay time uncertainties due to noise and the interconnect worst-case design.
Microstructure evolution during electromigration in eutectic SnPb solder bumps
(2004-08-01)
Lu, CM
;
Shao, TL
;
Yang, CJ
;
Chen, C
;
材料科學與工程學系
A technique has been developed to facilitate analysis of the microstructural evolution of solder bumps after current stressing. Eutectic SnPb solders were connected to under-bump metallization (UBM) of Ti/Cr-Cu/Cu and pad metallization of Cu/Ni/Au. It was found that the Cu6Sn5 compounds on the cathode/chip side dissolved after the current stressing by 5 x 10(3) A/cm(2) at 150 degreesC for 218 h. However, on the anode/chip side, they were transformed into (NixCu1-x)(3)Sn-4 in the center region of the UBM, and they were converted into (Cu-y,Ni1-y)(6)Sn-5 on the periphery of the UBM. For both cathode/substrate and anode/substrate ends, (Cu-y,Ni1-y)(6)Sn-5 compounds were transformed into (Ni-x,Cu1-x)(3)Sn-4. In addition, the bumps failed at cathode/chip end due to serious damage of the UBM and the Al pad. A failure mechanism induced by electromigration is proposed in this paper.
The performance of the number of vehicles in a dynamic connecting transport AMHS
(2005-06-01)
Lin, JT
;
Wang, FK
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Yang, CJ
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工業工程與管理學系
;
Department of Industrial Engineering and Management
A new concept of the dynamic connecting transport automated material handling system (AMHS) is proposed. This paper analyses the performance of the number of vehicles in a dynamic connecting transport AMHS in a simplified 300mm wafer fab. Discrete-event simulation models are developed in e-M Plant(TM) to study the system performance. To avoid congestion or idle time in the intrabay system, the control of the upper limit or the lower limit on the number of vehicles can be the feasible solution. Thus, four strategies are identified and their performances are also investigated. In addition, several different operation environments such as the flow rate and the product-mix are used to investigate the performance of the dynamic connecting transport AMHS.
Trench gap-tilling copper by ion beam sputter deposition
(2006-05-10)
Han, S
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Lee, TL
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Yang, CJ
;
Shih, HC
;
材料科學與工程學系
The ion beam sputter deposition (IBSD) and electroless plating techniques have been combined to achieve the precipitation of Cu onto an amorphous (a)-TaN diffusion barrier layer in order to accomplish the ultralarge-scale-integrated interconnect metallization. The copper-filled specimens were annealed at various temperatures in a reduced atmosphere. The preferred orientation was analyzed by X-ray diffraction, and field emission scanning electron microscopy was used to elucidate the growth mechanism of the trench-filled electroless deposited Cu film on the Cu seeded layer by IBSD. The Cu(1 1 1) texture was strengthened by annealing at 300 degrees C for 1 h. The surface roughness increased notably with increasing annealing temperature. The electrical resistivity of the as-deposited copper film (3.05 mu Omega cm) decreased with increasing annealing temperature. The major contribution of this study is to successfully combine the techniques of IBSD and electroless plating for the Cu gap-filling of submicron trenches with an excellent step coverage. (c) 2006 Published by Elsevier B.V.
Turnaround phenomenon of threshold voltage shifts in amorphous silicon thin film transistors under negative bias stress
(2000-10-01)
Huang, CY
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Tsai, JW
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Teng, TH
;
Yang, CJ
;
Cheng, HC
The turnaround phenomenon of threshold voltage shifts is investigated in thin film transistors (TFTs) with different defect densities of hydrogenated amorphous silicon (a-Si:H) films and compositions of SiNx. It was found that TFTs with high-defect-density a-Si:H films and N-rich SiNx gate exhibit the turnaround phenomenon while TFTs with other conditions of a-Si:H and SiNx films do not. Results reveal that the turnaround phenomenon is greatly influenced by charge traps in SiNx and state creation in the a-Si:H layer. When state creation is dominant at low bias stress, the turnaround phenomenon occurs. In contrast, if charge trapping is dominant at low bias stress, the turnaround phenomenon does not occur.