Browsing by Author "Yang, Che-Ming"

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Large paleo-rockslide induced by buckling failure at Jiasian in Southern Taiwan
(1970-01-01)
Yang, Che-Ming
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Kang, Keng-Hao
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Yang, Shun-Hsing
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Li, Kuo-Wei
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Wang, Hui-Jung
The major regions of Taiwan consist of high-relief terrain exposed to frequent typhoons and earthquakes. Recently, thousands of potential large-scale landslides have been delineated via remote sensing analysis and field surveys. However, little attention has been paid to the stability of colluvium, which is a potential hazard. This study investigated a paleo-rockslide site in detail and proposes a geological model to explain the failure mechanism. The studied area is in Jiasian, Southern Taiwan, and the site is a dip slope consisting of Miocene sedimentary rocks. Detailed topographic features, including residual slip surfaces, platforms, scarps, and colluviums, are identified using the slope map of a 1- m airborne remotely sensed digital elevation model. Platforms beneath the residual slip surfaces represent the topographic features of the paleo-rockslide, an interpretation validated by field works and core analysis. The platforms consist of a displaced rock mass (DRM) with a gentle bedding dip angle and interbedded structure that has been preserved. A geological model is established according to the data compiled; outcrops of DRM and colluviums on bedrock were delineated in the geological map and profiles. Outcrops of shear off, buckling, and compressive ridges within the alternating sandstone and shale are distributed at the toe of the residual slip surfaces. A geological model with identified topographic features is adopted to establish the geomorphological evolution of the site. A buckling-induced rockslide model in the dip slope of the interbedded layers is proposed, and potential future slope failure scenarios can be evaluated using the geomorphological evolution model.
On-chip detection circuit for protection design in display panel against electrical fast transient (EFT) disturbance
(2011)
Yen, Cheng-Cheng
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Ker, Ming-Dou
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Lin, Wan-Yen
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Yang, Che-Ming
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Chen, Shih-Fan
A new on-chip detection circuit is proposed for electrical fast transient (EFT) protection design in a display system. For microelectronic products, electrical transient disturbances often cause upset or frozen states under the IEC test standard. The output signal of the proposed detection circuit can be used as a firmware index to execute system automatic recovery operations and to release the EFT-induced locked states in display panels. The circuit function to detect positive or negative electrical transients has been investigated in HSPICE simulation and verified in silicon chip. The experimental results have confirmed successful circuit performance under EFT tests. With hardware/firmware co-design, the immunity of a display system against electrical transient disturbance has been significantly improved.
Protection Design Against System-Level ESD Transient Disturbance on Display Panels
(2010-01-01)
Ker, Ming-Dou
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Lin, Wan-Yen
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Yen, Cheng-Cheng
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Yang, Che-Ming
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Chen, Tung-Yang
A hardware/firmware system co-design has been proposed in this work to protect display electronic products against system-level electrostatic discharge (ESD) transient disturbance. By including transient detection circuit, the firmware can execute system recovery procedure to recover all electrical functions under system-level ESD tests. The transient detection circuit is designed to detect different positive and negative fast electrical transients and verified in a 0.13 mu m CMOS process. The experimental results have confirmed that the proposed hardware/firmware design can successfully improve the susceptibility of display products against system level ESD zapping.