Browsing by Author "Yang, Cheng-Chen"

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A Dual-Level Dual-Phase Pulse-Width Modulation Class-D Amplifier with 0.001% THD, 112 dB SNR
(2014-01-01)
Yang, Shang-Hsien
;
Yang, Yuan-Han
;
Chen, Ke-Horng
;
Hung, Chung-Chih
;
Wey, Chin-Long
this paper presents a dual-level dual-phase pulse-width modulation (DLDP PWM) Class-D audio amplifier circuit which enhance amplifier linearity and reduce distortion. The proposed DLDP PWM Class-D audio amplifier includes two sets of non-overlapping triangular waves, each at its respectful offset levels. Each set of triangular waves is composed of two 180 degrees out-of-phase triangular waves. The differential power stage consists of 8 power transistors, with voltage swings up to +/- 6V. Simulated results shows that the proposed DLDP PWM Class-D audio amplifier features an SNR up to 105 dB, and the THD is suppressed below 0.001 %, with the 3rd harmonic below -102 dBV.
A Low THD Clock-Free Class-D Audio Amplifier with an Increased Damping Resistor and Cross Offset Cancellation Technique
(2014-01-01)
Chou, Ying-Wei
;
Chien, Meng-Wei
;
Chen, Shin-Chieh
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
an increased damping resistor (IDR) replaces high-order loop filter to simply reduce the total harmonic distortion (THD) of Class-D audio amplifier. Besides, cross offset cancellation (COC) technique minimizes the system offset voltage to avoid dc current flows to the speaker in the bridge tied load (BTL) structure. Furthermore, variable switching frequency characteristic in self-oscillating modulation spreads the electro-magnetic interference (EMI) impact out on the output frequency spectrum. Experimental results demonstrate that the proposed Class-D amplifier can deliver 0.55W to the 8 Omega load with a 3.3V supply voltage with 150-nm CMOS process. The power efficiency is over 90% and the output THD is smaller than 0.01% (80dB).
A Pseudo Fixed Switching Frequency 2kHz/A in Optimum On-Time Control Buck Converter with Predicting Correction Technique for EMI Solution
(2014-01-01)
Chen, Wei-Chung
;
Lin, Kuei-Liang
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
;
Tsai, Tsung-Yen
This paper repots an optimum on-time (OOC) control with predicting correction technique (PCT) for ripple-based buck converter. The switching frequency (F-SW) variation is analyzed with completely considering the parasitic resistances of the components and devices. The proposed converter achieved nearly constant switching frequency over a wide load range without extra clock controlled circuits and current sensing circuits. The parameters of the parasitic resistances almost cause no influence and no restriction on F-SW performance. Actually, only the input voltage is necessary to predict the optimum on-time, and this work benefits the decease on total pin numbers. The simulation results demonstrate 0.375% Delta F-SW/F-SW and 2kHz/A Delta F-SW/Delta I-LOAD over 1.5A load current change. Consequently, pseudo constant F-SW with known noise spectrum strongly benefits the solution of electromagnetic interference (EMI) issue for system-on-chip (SoC).
High-PF and Ultra-Low-THD Power Factor Correction Controller by Sinusoidal-Wave Synthesis and Optimized THD Control
(2013)
Chang, Chih-Wei
;
Ni, Chia-Lung
;
Tsai, Jen-Chieh
;
Chen, Yi-Ting
;
Chen, Chun-Yen
the proposed sinusoidal-wave synthesis (SWS) and the optimized THD control (OTC) improve power factor (PF) and total harmonic distortion (THD) over a wide line voltage range. The SWS detects the input line root-mean-square (rms) voltage to generate the digital equivalent code to the OTC for optimizing the THD by tuning the on-time value. Besides, the SWS and the OTC provide a feedforward path to reduce the ripple of the feedback voltage for further improving the THD. Therefore, the PFC converter can keep high PF and low THD over a wide line voltage. Experimental results demonstrate the PF is higher than 0.99 and the THD is 1.7% at V-AC of 90 - 110V by the test circuit fabricated in TSMC 800V UHV process.
Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings
(2013-11-01)
Peng, Shen-Yu
;
Huang, Tzu-Chi
;
Lee, Yu-Huei
;
Chiu, Chao-Chang
;
Chen, Ke-Horng
This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-power processor designs. The proposed iDVS technique is fully compatible with conventional DVS scheduler algorithms. An additional computer aided design-based design flow was embedded in a standard cell library to implement the iDVS-based processor in highly integrated system-on-a-chip applications. The lattice asynchronous self-timed control digital low-dropout regulator with swift response and low quiescent current was also utilized to improve iDVS voltage transition response. Results show that the iDVS-based processor with the proposed adaptive instruction cycle control scheme can efficiently perform millions of instructions per second during iDVS transition. The iDVS-based digital signal processor chip was implemented in a HH-NEC 0.18-mu m standard complementary metal-oxide semiconductor. Measurement results show that the voltage tracking speed with 11.6 V/mu s saved 53% power.