Browsing by Author "Yang, Chi-Heng"

Now showing 1 - 5 of 5

A Fully Parallel BCH Codec with Double Error Correcting Capability for NOR Flash Applications
(2012)
Chu, Chia-Ching
;
Lin, Yi-Min
;
Yang, Chi-Heng
;
Chang, Hsie-Chia
;
電子工程學系及電子研究所
A double error correcting (DEC) BCH codec is designed for NOR flash memory systems to improve reliability. Due to the latency constraint less than 10 ns, the fully parallel architecture with huge hardware cost is utilized to process both the encoding and decoding scheme within one clock cycle. Notice that encoder and decoder will not be activated simultaneously in NOR flash applications, so we combine the encoder and syndrome calculator based on the property of minimal polynomials in order to efficiently arrange silicon area. Furthermore, a new error location polynomial is developed to reduce the number of constant finite filed multipliers (CFFMs) in Chien search. According to 90 nm CMOS technology, our propose DEC BCH codec can achieve 2.5 ns latency with 41,705 mu m(2) area.
A MPCN-Based Parallel Architecture in BCH Decoders for NAND Flash Memory Devices
(2011-10-01)
Lin, Yi-Min
;
Yang, Chi-Heng
;
Hsu, Chih-Hsiang
;
Chang, Hsie-Chia
;
Lee, Chen-Yi
According to large-page-size and random-bit-error characteristics, long-block-length Bose-Chaudhuri-Hochquenghem (BCH) decoders are applied to realize error correction in NAND Flash memory devices. To accelerate the decoding process in an area-efficient architecture, a parallel architecture with minimal polynomial combinational network (MPCN) for long BCH decoders is presented in this brief. The proposed design utilizes MPCNs to replace constant finite-field multipliers, which dominate the hardware complexity of the high-parallel Chien search architecture. Furthermore, both the syndrome calculator and the Chien search can be merged by exploiting our MPCN-based architecture, leading to significant hardware complexity reduction. From the synthesis results in the 90-nm CMOS technology, the MPCN-based joint syndrome calculation and Chien search has 46.7% gate count saving for parallel-32 BCH (4603, 4096; 39) decoder in contrast with the straightforward design.
An Area-Efficient BCH Codec with Echelon Scheduling for NAND Flash Applications
(2013-01-01)
Yang, Chi-Heng
;
Chen, Yi-Hsun
;
Chang, Hsie-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents an area-efficient BCH codec with echelon scheduling for NAND flash memory systems. In our proposed design, instead of the common inversionless Berlekamp-Massey algorithm, the BM algorithm using a low-complexity 2-stage composite field divider is applied in the key equation solver. Moreover, by making use of the fact that the degree of error locator polynomial increases at most by 1 in each iteration, an echelon scheduling architecture with 6 finite field multipliers is presented. After implemented in UMC 1P9M 90 nm process, the proposed codec can achieve 385 MHz and 3.08 Gbit/s throughput with 147.8K gate-count from post-layout simulation results.
An Efficient BCH Decoder with 124-bit Correctability for Multi-Channel SSD Applications
(2012)
Tsai, Hung-Yuan
;
Yang, Chi-Heng
;
Chang, Hsie-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a low latency and area-efficient architecture for key equation solver (KES) in decoding BCH codes. We modify simplified inversionless Berlekamp-Massey (SiBM) algorithm by rescheduling initial value and removing the idle part during computation. Compared with the original SiBM algorithm, our new architecture implemented in BCH (18244, 16384;124) code can save 42% gate-count within t cycles. Moreover, the proposed KES can simultaneously support 8channel syndrome generators and Chien search logics to achieve 12.6Gb/s throughput under 198MHz operation frequency.
An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability
(2015-07-01)
Yang, Chi-Heng
;
Lin, Yi-Min
;
Chang, Hsie-Chia
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
This paper presents an area-efficient architecture of arbitrary error correction Bose-Chaudhuri-Hocquenghem codec for NAND flash memory. By factorizing the generator polynomial into several minimal polynomials and utilizing linear feedback shift registers based on minimal polynomials, our reconfigurable design cannot only support multiple error correcting capabilities at a few extra cost, but also merge the encoder and syndrome calculator for efficiently reducing hardware complexity. After being implemented in CMOS 65-nm technology, the test chip supporting t = 1-24 bits can achieve 1.33-Gb/s measured throughput with 73k gate-count while another design supporting t = 60-84 bits can provide 1.60-Gb/s synthesized throughput with 168.6k gate-count.