Browsing by Author "Yang, Chia-Hsiang"

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A 0.5V 1.27mW Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia
(2014-01-01)
Tang, Kea-Tiong
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Chiu, Shih-Wen
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Shih, Chung-Hung
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Chang, Chia-Ling
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Yang, Chia-Min
A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip
(2018-10-01)
Chou, Ting-I
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Chang, Kwuang-Han
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Jhang, Jia-Yin
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Chiu, Shih-Wen
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Wang, Guoxing
Miniature gas detection system is desirable for many applications. In this brief, we propose a fully integrated nose-on-a-chip for mobile phones and wearable devices. The chip has 36 on-chip sensors, a 36-channel adaptive interface with an integrated programmable amplifier, a four-channel frequency readout interface, one on-chip temperature sensor, a successive approximation analog-to-digital converter, a scalable learning kernel cluster, and a reduced instruction set computing core with low-voltage static random-access memory. This chip is fabricated using the TSMC 180-nm CMOS process and consumes 2.6 mW at 1 V. on-chip temperature and humidity sensors are included in this system for acquiring environmental information. An environmental compensation algorithm based on common principal components analysis is also implemented for high-accuracy odor classification. This fully integrated nose-on-a-chip provides promising results for odor detection and classification for use in mobile and wearable device applications.
A 135-mW Fully Integrated Data Processor for Next-Generation Sequencing
(2017-12-01)
Wu, Yi-Chung
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Chang, Chia-Hua
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Hung, Jui-Hung
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Yang, Chia-Hsiang
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分子醫學與生物工程研究所
Next-generation sequencing (NGS) enables high-throughput sequencing, in which short DNA fragments can be sequenced in a massively parallel fashion. However, the essential algorithm behind the succeeding NGS data analysis, DNA mapping, is still excessively time consuming. DNA mapping can be partitioned into two parts: suffix array (SA) sorting and backward searching. Dedicated hardware designs for the less-complex backward searching have been proposed, but feasible hardware for the most complicated part, SA sorting, has never been explored. Based on the memory-efficient sBWT algorithm, this work is the first integrated NGS data processor for the entire DNA mapping. The k-ordered Ferragina and Manzini index used in the sBWT algorithm is leveraged to improve storage capacity and reduce hardware complexity. The proposed NGS data processor realizes the sBWT algorithm through bucket sorting, suffix grouping, and suffix sorting circuits. Key design parameters are analyzed to achieve the optimal performance with respect to hardware cost and execution time. Fabricated in 40-nm CMOS, the NGS data processor dissipates 135 mW at 200 MHz from a 0.9-V supply. With 1-GB external memory, the chip can analyze human DNA within 10 min. This work achieves 43 065x and 8 971x [3208x and 402x] higher energy efficiency (throughput-to-area ratio) than the high-end CPU and GPU solutions, respectively.
A 135mW Fully Integrated Data Processor for Next-Generation Sequencing
(2017-01-01)
Wu, Yi-Chung
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Hung, Jui-Hung
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Yang, Chia-Hsiang
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交大名義發表
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National Chiao Tung University
A 2.17-mW Acoustic DSP Processor With CNN-FFT Accelerators for Intelligent Hearing Assistive Devices
(2020-08-01)
Lee, Yu-Chi
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Chi, Tai-Shih
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Yang, Chia-Hsiang
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電機工程學系
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Department of Electrical and Computer Engineering
This article presents an acoustic DSP processor containing a neural network core for intelligent hearing assistive devices. The processor includes the accelerators for convolutional neural networks (CNNs) and fast Fourier transform (FFT). The CNN-based speech enhancement algorithm predicts the desired mask for the Fourier spectrogram of the speech signal to enhance speech intelligibility. Several design techniques are applied to enable efficient hardware mapping. The computational complexity for the CNN can be reduced by 23.6% by frame sharing, and a fast mask generation + partial sums pre-computation technique further reduces output latency by up to 64%. The size of the memory for the model is reduced by 75% using weight quantization. FFT is implemented by leveraging the packing algorithm to reduce the computational complexity by 43%. Reconfigurable processing elements are shared to support both FFT and CNN, realizing a saving in the area of 42%. In addition, input sharing and output sharing are used to, respectively, reduce data movements by 94% and 75%. A reordered FFT structure also eliminates up to 256 multiplexers. Fabricated in a 40-nm CMOS technology, the chip's core area is 4.2 mm(2) and the power dissipation is 2.17 mW at a clock frequency of 5 MHz from a 0.6-V supply. The embedded CNN accelerator supports both convolutional and fully connected (FC) layers and achieves a comparable energy efficiency with state-of-the-art CNN accelerators, despite the flexibility for FFT. The speech intelligibility is enhanced by up to 41% in the low SNR regime.
A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices
(2019-01-01)
Lee, Yu-Chi
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Chi, Tai-Shih
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Yang, Chia-Hsiang
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電機工程學系
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Department of Electrical and Computer Engineering
This paper proposes an acoustic DSP processor with a neural network core for speech enhancement. Accelerators for convolutional neural network (CNN) and fast Fourier transform (FFT) are embedded. The CNN-based speech enhancement algorithm takes the speech signals spectrogram as the model's input, and predicts the desired mask of speech to enhance speech intelligibility after passing through the CNN model. An array of multiply-accumulator (MAC) and coordinate rotation digital computer (CORDIC) engines are deployed to efficiently compute linear and nonlinear functions. Hardware sharing is applied to reduce hardware area by leveraging the high similarity between CNN and FFT computations. The proposed DSP processor chip is fabricated in a 40-nm CMOS technology with a core area of 4.3 mm(2). The chip's power dissipation is 2.17 mW at an operating frequency of 5 MHz. The CNN accelerator supports both convolutional and fully-connected layers and achieves an energy efficiency of 1200-to-2180 GOPS/W, despite the flexibility for FFT. The speech intelligibility can be enhanced by up to 41% under low SNR conditions.
A 2x2-16x16 Reconfigurable GGMD Processor for MIMO Communication Systems
(2018-01-01)
Chiang, Chih-Hsuan
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Huang, Shuo-An
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Chen, Chiao-En
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Yang, Chia-Hsiang
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電子工程學系及電子研究所
The generalized geometric mean decomposition (GGMD) is a recently proposed matrix decomposition which can be viewed as a computationally efficient counterpart of the conventional geometric mean decomposition (GMD). As the GMD is the core algorithm in many high performance precoders and equalizers such as the Tomlinson-Harashima precoder and decision feedback equalizer, GGMD facilitates a more computationally efficient implementation while exhibiting identical performance. This work presents the first GGMD processor in the open literature, supporting various matrix sizes by leveraging the reconfigurable processing element (PE) using coordinate rotation digital computers (CORDICs). The implemented GGMD processor supports matrix sizes of 2(n) which ranges from 2 x 2 to 16 x 16, and the throughput performance is maximized through a PE array architecture. The chip integrates 326.9K gates in an area of 1.65 mm(2) in a 90-nm CMOS technology with the maximum throughput achieving 450K matrices/sec for a 16 x 16 matrix at 125 MHz. It dissipates 20.7-28.5 mW at 125 MHz from a 1V supply. Compared to previous GMD designs, this work supports a larger MIMO system with lower hardware complexity and power consumption.
A 5.4 mu W Soft-Decision BCH Decoder for Wireless Body Area Networks
(2014-09-01)
Yang, Chia-Hsiang
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Huang, Ting-Ying
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Li, Mao-Ruei
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Ueng, Yeong-Luh
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交大名義發表
This paper presents an IEEE 802.15.6 compliant soft-decision BCH decoder for energy-constrained wireless body area networks. The proposed soft-decision decoder (SDD) provides a 1 dB coding gain compared to the hard-decision decoder (HDD). The improvement in BER performance can translate into power savings at the transmitter. The energy dissipation and area of the soft-decision BCH decoder is minimized by jointly considering the algorithm, architecture, and circuit parameters. An early termination strategy is proposed to reduce the number of redundant test patterns. Probabilistic sorting is proposed to determine the test patterns, and its hardware complexity is only 54.7% of the conventional sorting method. The HDD kernel is implemented by adopting the Peterson rule, reducing the area by 44.2%. A pass-transistor logic based Chien search circuit consumes 33.3% less energy compared to the standard-cell based implementation. The chip is designed to operate at the minimum energy point of 0.29 V, yielding an energy reduction of 94% compared to a direct-mapped SDD at SNR = 5 dB. Fabricated in 90 nm CMOS, the chip dissipates 5.4 mu W at 500 kHz, achieving a throughput of 6.38 Mbps.
A 501mW 7.61Gb/s Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MIMO Systems
(2017-01-01)
Chen, Yan-Tong
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Cheng, Chung-Chao
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Tsai, Tsung-Lin
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Sun, Wei-Cheng
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Ueng, Yeong-Luh
This work presents the first integration of a message-passing detector (MPD) and a polar decoder. A soft-output MPD, which is essential to approach the channel capacity, is first proposed. Compared to the state-of-the-art design, the proposed MPD achieves a 6.9x higher throughput with 49% lower energy, despite the soft outputs. The proposed polar decoder achieves a 1.35x higher throughput with comparable energy. The chip delivers a throughput of 7.61Gb/s for massive MIMO systems with up to 128 antennas and 32 users.
A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios
(2012-09-01)
Yu, Tsung-Han
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Yang, Chia-Hsiang
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Cabric, Danijela
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Markovic, Dejan
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電子工程學系及電子研究所
"A digital baseband cognitive radio spectrum sensing processor with 200-kHz resolution over 200-MHz bandwidth is integrated in 1.64 mm in 65-nm(2) CMOS. The processor uses adaptive channel-specific threshold and sensing time to achieve detection probability >= 0.9 and false-alarm probability <= 0.1 for -5-dB SNR and adjacent-band interferers of 30-dB INR within a 50-ms sensing time. The chip power and area are minimized by jointly considering algorithm, architecture, and circuit parameters. The chip dissipates 7.4 mW for a 200-MHz sensing bandwidth, which is a 22x reduction in power per sensing bandwidth compared with prior work."
A 794Mbps 135mW Iterative Detection and Decoding Receiver for 4x4 LDPC-Coded MIMO Systems in 40nm
(2015)
Wu, Wei-Hsuan
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Sun, Wei-Cheng
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Yang, Chia-Hsiang
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Ueng, Yeong-Luh
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交大名義發表
A low-density parity-check (LDPC)-coded multiple-input multiple-output (MIMO) systems with iterative detection and decoding (IDD) chip is integrated in 1.33mm(2) in 40nm CMOS. The maximum gross throughput is 794Mb/s for a 4x4 16-QAM configuration at 288MHz. The chip dissipates 135mW at 0.9V, achieving an energy efficiency of 170pJ/bit. Compared to non-IDD receivers, composed of state-of-the art MIMO detectors and LDPC decoders, this work achieves even higher area and energy efficiencies, despite the improved error performance.
A 98.6 mu W Acoustic Signal Processor for Fully-Implantable Cochlear Implants
(2016)
Liu, Hao-Min
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Lin, Yung-Jen
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Lee, Yu-Chi
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Lee, Cheng-Yen
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Yang, Chia-Hsiang
This paper presents a low-power acoustic signal processor for fully-implantable cochlear implants. The developed processor supports adaptive beamforming, frequency-domain analysis, envelope detection, channel combination, and magnitude compression. Power and area are minimized by leveraging dedicated real-valued FFT, register count minimization, data allocation optimization, hardware complexity reduction, and minimum-energy-point operation. Compared to complexvalued FFT, real-valued FFT achieves 44.36% power reduction. Register count minimization and data allocation for FFT output reordering yields 28.07% and 27.09% area and power reduction, respectively. Envelope detection and log-compression are realized by hardware-efficient CORDIC engines. The processor is scalable to support various numbers of channels. This chip is implemented in 90-nm CMOS and the core area is 0.47 mm(2). It dissipates 98.6 mu W at 50 kHz, 0.33 V for a latency of 3 ms.
A Bone-Guided Cochlear Implant CMOS Microsystem Preserving Acoustic Hearing
(2017-01-01)
Qian, Xin-Hong
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Wu, Yi-Chung
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Yang, Tzu-Yi
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Cheng, Cheng-Hsiang
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Chu, Hsing-Chien
In this paper, a bone-guided cochlear implant (BGCI) SOC microsystem is proposed and designed. The BGCI microsystem uses four or more electrodes placed on the bone surface of the cochlea and one on the round window to preserve partially the acoustic hearing. The external SOC of the BGCI processes the acoustic signals and generates stimulation patterns and command that are transmitted to the implanted chip through the 13.56MHz wireless power and bidirectional data telemetry. The implanted chip with 4-channel high-voltage-tolerant stimulator generates biphasic stimulation currents up to 800 mu A and sends back the power indication and electrode impedance error signals to the external SOC. Electrical tests on the fabricated BGCI has been performed. The in-vivo animal tests on guinea pigs has shown the evoked Wave III of EABR waveforms. The proposed BGCI can be applied to patients with high-frequency hearing loss, tinnitus, and dizziness.
A Flexible Geometric Mean Decomposition Processor for MIMO Communication Systems
(2017-02)
Tsai, Yu-Cheng
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Chen, Chiao-En
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Yang, Chia-Hsiang
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a geometric-mean-decomposition (GMD) processor for multiple-input multiple-output (MIMO) communication systems. The proposed GMD pro cessor has a flexible architecture that supports channel matrices of arbitrary dimensions. A complex-valued bi-diagonalization is proposed at the preprocessing stage, which substantially reduces the overall hardware complexity. The proposed GMD processor naturally supports an economic channel state information (CSI) feedback mechanism, rendering it highly suitable for frequency-division- duplexing (FDD) systems. To illustrate the performance of the proposed architecture, we demonstrate an efficient implementation supporting 2 to 8 spatial streams in a 90-nm CMOS technology. The latency constraint of 16 mu s specified in the 802.11ac standard is adopted for this hardware realization. The chip integrates 437.7 K gates in 1.830 x 1.829 mm(2) and dissipates 125.5 mW at 66.67 MHz from a 1 V supply. Compared with the existing GMD implementations, this work supports GMD for matrices of larger dimensions with comparable silicon area, despite the added spatial information feedback capability. Index Terms-CORDIC, geometric mean decomposition
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control
(2014-01-01)
Chen, Wei-Ming
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Chiueh, Herming
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Chen, Tsan-Jieh
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Ho, Chia-Lun
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Jeng, Chi
An 8-channel closed-loop neural-prosthetic SoC is presented for real-time intracranial EEG (iEEG) acquisition, seizure detection, and electrical stimulation in order to suppress epileptic seizures. The SoC is composed of eight energy-efficient analog front-end amplifiers (AFEAs), a 10-b delta-modulated SAR ADC (DMSAR ADC), a configurable bio-signal processor (BSP), and an adaptive high-voltage-tolerant stimulator. A wire-less power-and-data transmission system is also embedded. By leveraging T-connected pseudo-resistors, the high-pass (low-pass) cutoff frequency of the AFEAs can be adjusted from 0.1 to 10 Hz (0.8 to 7 kHz). The noise-efficiency factor (NEF) of the AFEA is 1.77, and the DMSAR ADC achieves an ENOB of 9.57 bits. The BSP extracts the epileptic features from time-domain entropy and frequency spectrum for seizure detection. A constant 30-mu A stimulus current is delivered by closed-loop control. The acquired signals are transmitted with on-off keying (OOK) modulation at 4 Mbps over the MedRadio band for monitoring. A multi-LDO topology is adopted to mitigate the interferences across different power domains. The proposed SoC is fabricated in 0.18-mu m CMOS and occupies 13.47 mm(2). Verified on Long Evans rats, the proposed SoC dissipates 2.8 mW and achieves high detection accuracy 92% within 0.8 s.
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic SoC for Real-Time Epileptic Seizure Control
(2013-01-01)
Chen, Wei-Ming
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Chiueh, Herming
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Chen, Tsan-Jieh
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Ho, Chia-Lun
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Jeng, Chi
A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia
(2014-12-01)
Chiu, Shih-Wen
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Wang, Jen-Huo
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Chang, Kwuang-Han
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Chang, Ting-Hau
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Wang, Chia-Min
Ventilator-associated pneumonia (VAP) still lacks a rapid diagnostic strategy. This study proposes installing a nose-on-a-chip at the proximal end of an expiratory circuit of a ventilator to monitor and to detect metabolite of pneumonia in the early stage. The nose-on-a-chip was designed and fabricated in a 90-nm 1P9M CMOS technology in order to downsize the gas detection system. The chip has eight on-chip sensors, an adaptive interface, a successive approximation analog-to-digital converter (SAR ADC), a learning kernel of continuous restricted Boltzmann machine (CRBM), and a RISC-core with low-voltage SRAM. The functionality of VAP identification was verified using clinical data. In total, 76 samples infected with pneumonia (19 Klebsiella, 25 Pseudomonas aeruginosa, 16 Staphylococcus aureus, and 16 Candida) and 41 uninfected samples were collected as the experimental group and the control group, respectively. The results revealed a very high VAP identification rate at 94.06% for identifying healthy and infected patients. A 100% accuracy to identify the microorganisms of Klebsiella, Pseudomonas aeruginosa, Staphylococcus aureus, and Candida from VAP infected patients was achieved. This chip only consumes 1.27 mW at a 0.5 V supply voltage. This work provides a promising solution for the long-term unresolved rapid VAP diagnostic problem.
A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications
(2014-09-01)
Cheng, Chung-Chao
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Yang, Jeng-Da
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Lee, Huang-Chang
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Yang, Chia-Hsiang
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Ueng, Yeong-Luh
This paper presents a normalized probabilistic min-sum algorithm for low-density parity-check (LDPC) codes, where a probabilistic second minimum value, instead of the true second minimum value, is used to facilitate fully parallel decoder realization. The comparators in each check-node unit (CNU) are connected through an interconnect network based on a mix of tree and butterfly networks such that the routing and message passing between the variable-node units (VNUs) and CNUs can be efficiently realized. In order to further reduce the hardware complexity, the normalization operation is realized in the VNU rather than in the CNU. An early termination scheme is proposed in order to prevent unnecessary energy dissipation for both low and high signal-to-noise-ratio regions. The proposed techniques are demonstrated by implementing a (2048, 1723) LDPC decoder using a 90 nm CMOS process. Post-layout simulation results show that the decoder supports a throughput of 45.42 Gbps at 199.6 MHz, achieving the highest throughput and throughput-to-area ratio among comparable works based on a similar or better error performance.
A Hardware-Efficient VLSI Architecture for Hybrid Sphere-MCMC Detection
(2011-01-01)
Yuan, Fang-Li
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Yang, Chia-Hsiang
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Markovic, Dejan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a hybrid soft-output MIMO detector that searches reliable soft-information in both deterministic and probabilistic ways. The fixed-complexity sphere detector (FSD) is first applied to provide near maximum-likelihood (ML) solutions. The solutions are next used to initialize the Markov Chain Monte Carlo (MCMC) detector that uses parallel Gibbs samplers (GSs) for remaining candidate enumeration. A lowcomplexity VLSI architecture is proposed to demonstrate the feasibility of hardware realization for high-throughput applications. Simulation results indicate that the hybrid detector has a 2.3x complexity reduction and a 2x throughput improvement compared to individual soft-output FSD and MCMC detectors.
A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems
(2018-11-01)
Yeh, Chun-Yu
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Chu, Ting-Chung
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Chen, Chiao-En
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Yang, Chia-Hsiang
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電子工程學系及電子研究所
Millimeter-wave (mm-Wave) communication, operating from 30- to 300-GHz bands with wider available spectrum, has now emerged as a promising solution for future wireless systems. To reduce the hardware complexity of mm-Wave transceivers, beam-selection techniques combined with beamspace multiple-input multiple-output (MIMO) communications have been proposed in the literature. In such a system, beam selection is performed to exploit the near-sparse nature in the mm-Wave channel and, hence, is crucial to the system performance. This paper presents the world's first digital signal processing (DSP) architecture design for beam selection operation in an mm-Wave multi-user MIMO system. A computationally efficient beam-selection algorithm is first presented. Based on the proposed algorithm, a hardware-scalable beam selection processor is implemented using coordinate rotation digital computers arithmetic. To establish the validity of the concept, the proposed processor is implemented in a 40-nm CMOS technology, integrating 360k logic gates in an area of 0.5625 mm(2), while dissipating 44 mW at 266 MHz in an MU-MIMO system with 16 beams and 8 users.