Browsing by Author "Yang, FL"

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An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature
(2006-03-01)
Lee, W
;
Su, P
;
Chen, HY
;
Chang, CY
;
Su, KW
This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.
Hot-carrier-induced degradation for partially depleted SOI 0.25-0.1 mu m CMOSFET with 2-nm thin gate oxide
(2002-12-01)
Yeh, WK
;
Wang, WH
;
Fang, YK
;
Chen, MC
;
Yang, FL
Hot-carrier-induced degradation of partially depleted SOI CMOSFETs was investigated with respect to body-contact (BG-SOI) and floating-body (FB-SOI) for channel lengths ranging from 0.25 down to 0.1 mum with 2 nm gate oxide. It is found that the valence-band electron tunneling is the main factor of device degradation for the SOI CMOSFET. In the FB-SOI nMOSFET, both the floating body effect (FBE) and the parasitic bipolar transistor effect (PBT) affect the hot-carrier-induced degradation of device characteristics. Without apparent FBE on pMOSFET, the worst hot-carrier stress condition of the 0.1 mum FB-SOI pMOSFET is similar to that of the 0.1 mum BG-SOI pMOSFET.
Impact of post-deposition-annealing on the electrical characteristics of HfOxNy gate dielectric on Ge substrate
(2005-06-01)
Cheng, CC
;
Chien, CH
;
Chen, CW
;
Hsu, SL
;
Yang, MY
We systematically investigated the effect of post-deposition-annealing (PDA) on the electrical characteristics of Ge MOS capacitors with hafnium-oxynitride gate dielectric. The higher PDA temperature and longer PDA time was found to obtain the lower equivalent oxide thickness (EOT) of HfOxNy/Ge gate stack, however, with a larger hysteresis width. A lower EOT of 19.5 angstrom with a low leakage current of 1.8 x 10(-5) A/cm(2) at V-G = -1V was achieved after 600 degrees C annealing for 5 min. The improved capacitor properties after the PDA may be closely related to the different compositions and thicknesses of the resultant interfacial layers.