Browsing by Author "Yang, JN"

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A 1.5-V, 2.4GHz CMOS low-noise amplifier
(2000)
Yang, JN
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Lee, CY
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Hsu, TY
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Hsu, TR
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Wang, CC
A 2.4GHz low noise amplifier has been designed in a standard CMOS 0-35 um process. The transistor model is Bsim3 for 0.35um process. The amplifier provides a forward gain of 33dB with a noise figure only 0.92dB while drawing 17mw from a 1.5 V supply. Design simulation results are presented In this paper.
A 1.75GHz inductor-less CMOS low noise amplifier with high-Q active inductor load
(2001)
Yang, JN
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Cheng, YC
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Hsu, TY
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Hsu, TR
;
Lee, CY
A 1.75GHz CMOS inductor-less low noise amplifier with high-Q active inductor load using 0.35um. standard CMOS digital process is presented. In this low noise amplifier, the compact tunable high-Q active inductor load is connected to the common-gate configuration to improve the performance of the high power gain, low power consumption and simple matching characteristics. Not using any passive components is to reduce the area of chip and the complexity. HSPICE simulation has been performed to verify the performance of the designed low noise amplifier. It has been shown that the amplifier has a power gain of 24dB(S21), S11 of -31dB, S12 of -38.5dB and S22 of -21.4dB under 3.3V power supply with 9.3mW power consumption around at 1.75GHz center frequency. The experimental chip fabricated occupies 0.057x0.056 mm(2) chip area.
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications
(2006-06-01)
Chen, PL
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Chung, CC
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Yang, JN
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Lee, CY
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電子工程學系及電子研究所
This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscillator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD) and programmable divider are replaced with a digital arithmetic comparator and a DCO timing counter. The value in the DCO timing counter is separated into quotient and remainder vectors. A threshold region is set in the remainder vector to reduce the influence of jitter variation in frequency detection. The loop stability can be retained by cascading two DFC loops when the multiplication factor (N) is large. The proposed clock generator achieves a multiplication range from 4 to 13 888 with output peak-to-peak jitter less than 2.8% of clock period. A test chip for the proposed clock generator is fabricated in 0.18-mu m CMOS process with core area of 0.16 mm(2). Power consumption is 15 mW.@ 378 MHz with 1.8-V supply voltage.
A constant power consumption CMOS LC oscillator using improved high-Q active inductor with wide rining-range
(2004)
Wu, MJ
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Yang, JN
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Lee, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An improved CMOS high-Q active inductor and a constant power consumption oscillator with wide tuning-range are presented. The inductor using one feedback resistor results in a gain to improve the Q-value of the inductor and tune the inductance (L). Based on this inductor, a negative resistance LC-tuned oscillator with constant power consumption and wide tuning-range has been designed. The simulation results show that the improved active inductor can achieve the maximum Q-value of 3500. The power consumption of a constant value around 10mW exists in the oscillator. This oscillator also depicts a reasonable phase noise performance of -91dBc/Hz at 600 kHz from 0.8GHz to 3GHz range. Furthermore, the deviation of the phase noise is as small as 6dBc/Hz during this tuning-range.
A design of CMOS broadband amplifier with high-Q active inductor
(2003)
Yang, JN
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Cheng, YC
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Lee, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A CMOS broadband amplifier with high-Q active inductor using 0.25um CMOS process is presented In this broadband amplifier, the compact high-Q active inductor is connected to the common-gate configuration to improve the performance of the high power gain, wide bandwidth, low power consumption and simple matching characteristics. Not using any passive inductor components is to be reduced the area of chip and the complexity. Advance Design System (ADS) simulator has been performed to verify the performance of the designed broadband amplifier It has been shown that the amplifier has a 20dB(S21) power gain in -3dB bandwidth, S11 of -17dB, S22 of -21 dB and noise figure (NF) of 8dB, under 2.5 V power supply with 18mW power consumption.*
A novel RF CMOS active inductor
(2003-07-01)
Yang, JN
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Cheng, YC
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Lee, CY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A novel RF CMOS high Q-value active inductor is proposed in this work by using simple cascode RC feedback compensation technique. The performance of this active inductor has maximum Q-value about 1.2E6, inductance value from 3.5 nH to 4.5 nH and 3E-5Omega of minimum total equivalent loss, in the range of 1.2 GHz to 2 GHz.
Improving RF CMOS active inductor by simple loss compensation network
(2004-06-01)
Lee, CY
;
Yang, JN
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Cheng, YC
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An RF CMOS active inductor with a novel loss compensation circuit network is proposed. Performance of this active inductor can be improved by adding a novel network, which simultaneously reduces parallel and series losses. Consequently, this technique not only increases Q value, inductance, and operating frequency, but also reduces power consumption and circuit complexity. Simulation results show that better performance indices can be achieved, such as minimum total equivalent loss of 1 mOmega, maximum Q value about 3E5, and inductance value from 20 nH to 45 nH in the RF range of 0.6 GHz to 1.6 GHz. Power dissipation is around 1.76 mW under 2.5 V dc supply voltage.
Loss compensation in RF CMOS active inductor using a capacitor
(2004-12-01)
Yang, JN
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Wu, MJ
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Lee, CY
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Loss compensation in a RF CMOS active inductor with using a capacitor is proposed. This simple compensation technique yields a negative conductance characteristic that can compensate for the constant internal loss of active devices. Simulation results show that the inductor obtains a maximum Q-value of 1.2E8, an inductance value in the range of 50 nH to 450 nH, and a 1.4E-6 Omega of minimum total equivalent loss in the range of 0.6 GHz to 1.3 GHz.