Browsing by Author "Yang, Kai-Chun"

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A 60-nm-thick enhancement mode In0.65Ga0.35As/InAs/In0.65Ga0.35As high-electron-mobility transistor fabricated using Au/Pt/Ti non-annealed ohmic technology for low-power logic applications
(2016-02)
Fatah, Faiz Aizad
;
Lin, Yueh-Chin
;
Liu, Ren-Xuan
;
Yang, Kai-Chun
;
Lin, Tai-We
A 60-nm-thick E-mode In0.65Ga0.35As/InAs/In0.65Ga0.35As high-electron-mobility transistor (HEMT) was successfully fabricated and evaluated by using Au/Pt/Ti-based non-annealed ohmic technology for high-speed and low-power logic applications. The device exhibited a minimal SS of 69mV/decade, a lower DIBL of 30mV/V, an ION/IOFF ratio above 1.2 x 10(4) at V-DS = 0.5V and a high f(T) of 378GHz and f(max) of 214GHz at V-DS = 1.0V. These results demonstrate that non-annealed ohmic contacts can be used for fabricating E-mode In0.65Ga0.35As/InAs/In0.65Ga0.35As HEMTs with excellent electrical characteristics. The fabricated HEMTs are likely to find use in future high-speed and low-power logic applications. (C) 2016 The Japan Society of Applied Physics.
Evaluation of a 100-nm Gate Length E-Mode InAs High Electron Mobility Transistor With Ti/Pt/Au Ohmic Contacts and Mesa Sidewall Channel Etch for High-Speed and Low-Power Logic Applications
(2018-01-01)
Yao, Jing-Neng
;
Lin, Yueh-Chin
;
Hsu, Heng-Tung
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Yang, Kai-Chun
;
Hsu, Hisang-Hua
In this paper, a 100-nm gate length InAs high electron mobility transistor (HEMT) with non-alloyed Ti/Pt/Au ohmic contacts and mesa sidewall channel etch was investigated for high-speed and low-power logic applications. The device exhibited a low subthreshold swing (SS) of 63.3 mV/decade, a drain induced barrier lowering value of 23.3 mV/V, an I-on/I-off ratio of 1.34 x 10(4), a G(m,max)/SS ratio of 27.6, a current gain cut-off frequency of 439 GHz with a gate delay time of 0.36 ps, and an off-state gate leakage current of less than 1.6 x 10(-5) A/mm at V-DS = 0.5 V. These results demonstrated that the presence of non-annealed ohmic contacts with mesa sidewall etch process allowed the fabrication of InAs HEMTs with excellent electrical characteristics for high-speed and low-power logic applications.
Potential of Enhancement Mode In0.65Ga0.35As/InAs/In0.65Ga0.35As HEMTs for Using in High-Speed and Low-Power Logic Applications
(2015-01-01)
Fatah, Faiz Aizad
;
Lin, Yueh-Chin
;
Lee, Tsung-Yun
;
Yang, Kai-Chun
;
Liu, Ren-Xuan
In this study, a 60-nm enhancement-mode (E-mode) In0.65Ga0.35As/InAs/In0.65Ga0.35As high electron mobility transistor (HEMT) was developed, and its potential for use inhigh-speed and low-power logic applications was investigated. When the E-mode device was biased at a drain-source voltage of 0.5 V, it demonstrated a cutoff frequency of 169 GHz, drain-induced barrier lowering of 70 mV/V, minimum subthreshold swing of 67 mV/decade, and ION/IOFF ratio greater than 1.6 x 10(4). The high performance of the E-mode device is attributed to the use of a thin barrier layer along with Pt gate sinking technology. These results confirm that E-mode In0.65Ga0.35As/InAs/In0.65Ga0.35As HEMTs have great potential for use inhigh-speed and low-power logic applications. (C) 2015 The Electrochemical Society. All rights reserved.