Browsing by Author "Yang, Kai-Jiun"

Now showing 1 - 9 of 9

A 2.5-V 14-bit, 180-mW cascaded Sigma Delta ADC for ADSL2+ application
(2007-11-01)
Chang, Teng-Hung
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Dung, Lan-Rong
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Guo, Jwin-Yen
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Yang, Kai-Jiun
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電控工程研究所
This paper presents a sigma-delta (Sigma Delta) analog-to-digital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application. The core of the ADC is a cascaded 2-1-1 Sigma Delta modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2-MHz signal bandwidth, the ADC achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25 mu tm CMOS technology, in a 2.8 mm(2) active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.
An Interpretable Compression and Classification System: Theory and Applications
(2020-01-01)
Tseng, Tzu-Wei
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Yang, Kai-Jiun
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Kuo, C-C Jay
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Tsai, Shang-Ho
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電子工程學系及電子研究所
This study proposes a low-complexity interpretable classification system. The proposed system contains main modules including feature extraction, feature reduction, and classification. All of them are linear. Thanks to the linear property, the extracted and reduced features can be inversed to original data, like a linear transform such as Fourier transform, so that one can quantify and visualize the contribution of individual features towards the original data. Also, the reduced features and reversibility naturally endure the proposed system ability of data compression. This system can significantly compress data with a small percent deviation between the compressed and the original data. At the same time, when the compressed data is used for classification, it still achieves high testing accuracy. Furthermore, we observe that the extracted features of the proposed system can be approximated to uncorrelated Gaussian random variables. Hence, classical theory in estimation and detection can be applied for classification. This motivates us to propose using a MAP (maximum a posteriori) based classification method. As a result, the extracted features and the corresponding performance have statistical meaning and mathematically interpretable. Simulation results show that the proposed classification system not only enjoys significant reduced training and testing time but also high testing accuracy compared to the conventional schemes.
An LDPC Decoder with SNR Information
(2013-01-01)
Yang, Kai-Jiun
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Tsai, Shang-Ho
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Hsu, Heng-Chang
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電機工程學系
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Department of Electrical and Computer Engineering
In this work an LDPC decoder which complies with IEEE 802.11n is proposed and implemented. The code rate is 1/2 and the code length is 648. We used partially parallel structure to reduce the area. Additionally the SNR information is applied to improve the BER performance. Moreover the CNU and the BNU in the min-sum-correct algorithm were reordered so that the hardware complexity can be reduced, and early termination can be achieved at the first iteration. Furthermore the parity check matrix is reordered such that the latency of each iteration is reduced by 1/3. The proposed LDPC decoder can reach a throughput of 37 similar to 319Mbps with a core area of 5.3 mm(2) and power consumption 224mW in a TSMC 90nm process.
Compressed Sensing Recovery Algorithms and VLSI Implementation
(2013)
Lin, Kuan-Ting
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Yang, Kai-Jiun
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Lin, Pu-Hsuan
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Tsai, Shang-Ho
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電機工程學系
This paper proposes two recovery algorithms modified from subspace pursuit(SP) for compressed sensing problems. These algorithms can reduce the complexity of SP and maintain high recovery rate. Complexity analysis and simulation results are provided to demonstrate the improvements. Additionally this work has implemented the VLSI circuit APR of the proposed algorithm using TSMC 90 nm process. The target clock frequency is 100MHz, and the corresponding APR dimension is 11.69mm(2). Based on the post-layout simulation the average power consumption is 431 mW.
Maximum Likelihood and Soft Input Soft Output MIMO Detection at a Reduced Complexity
(2018-12-01)
Yang, Kai-Jiun
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Tsai, Shang-Ho
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper proposes an efficient pruning algorithm for MIMO detector, which not only achieves the same performance of the maximum likelihood (ML) decoder, but also massively reduces the number of visiting nodes. The proposed algorithm applies correct sorting order so that it achieves the same performance of the ML decoder. Thanks to the use of the correct ordering, both child and sibling nodes can be pruned efficiently. As a result, the number of visiting nodes is significantly reduced. To acquire properly sorted order, we propose fast sorting algorithms that generate the exact sorted sequence. Furthermore, the proposed schemes can be applied in SISO MIMO detector. The advantages of the proposed sphere decoder become more pronounced in high-order modulation schemes.
MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
(2013-04-01)
Yang, Kai-Jiun
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Tsai, Shang-Ho
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Chuang, Gene C. H.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an multipath delay commutator (MDC)-based architecture and memory scheduling to implement fast Fourier transform (FFT) processors for multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) systems with variable length. Based on the MDC architecture, we propose to use radix-N-s butterflies at each stage, where N-s is the number of data streams, so that there is only one butterfly needed in each stage. Consequently, a 100% utilization rate in computational elements is achieved. Moreover, thanks to the simple control mechanism of the MDC, we propose simple memory scheduling methods for input data and output bit/set-reversing, which again results in a full utilization rate in memory usage. Since the memory requirements usually dominate the die area of FFT/inverse fast Fourier transform (IFFT) processors, the proposed scheme can effectively reduce the memory size and thus the die area as well. Furthermore, to apply the proposed scheme in practical applications, we let N-s = 4 and implement a 4-stream FFT/IFFT processor with variable length including 2048, 1024, 512, and 128 for MIMO-OFDM systems. This processor can be used in IEEE 802.16 WiMAX and 3GPP long term evolution applications. The processor was implemented with an UMC 90-nm CMOS technology with a core area of 3.1 mm(2). The power consumption at 40 MHz was 63.72/62.92/57.51/51.69 mW for 2048/1024/512/128-FFT, respectively in the post-layout simulation. Finally, we analyze the complexity and performance of the implemented processor and compare it with other processors. The results show advantages of the proposed scheme in terms of area and power consumption.
On Performance of Sparse Fast Fourier Transform and Enhancement Algorithm
(2017-11-01)
Chen, Gui-Lin
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Tsai, Shang-Ho
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Yang, Kai-Jiun
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電機工程學系
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Department of Electrical and Computer Engineering
Sparse fast Fourier transform (FFT) is a promising technique that can significantly reduce computational complexity. However, only a handful of research has been conducted on precisely analyzing the performance of this new scheme. Accurate theoretical results are important for new techniques to avoid numerous simulations when applying them in various applications. In this study, we analyze several performance metrics and derive the corresponding closed-form expressions for the sparse FFT including 1) inter sparse interference due to nonideal windowing effects, 2) the probability of sparse elements overlapping, and 3) the recovering rate performance. From the analytical results, we gain insights and propose a novel mode-mean estimation algorithm for improving the performance. Simulation results are provided to show the accuracy of the derived results as well as the performance enhancement. We also show how to determine parameters to achieve the lowest computational complexity using these theoretical results.
Vehicular Signal Transmission Using Power Line Communications
(2012)
Chen, Yen-Chang
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Tsai, Shang-Ho
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Yang, Kai-Jiun
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Ho, Ping-Fan
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Tseng, Kuo-Feng
We propose a power line communication (PLC) system for transmitting control signals in vehicle through internal power lines, such that the internal wires can be reduced and the vehicles can be lighter. The signals from different devices are multiplexed and modulated to the power lines by the transmitter. In the receiver, first the noise within power lines are filtered. Afterwards the multiplexed signals are selectively extracted by specific codes which are minimally correlated. Finally the control signals are restored from the error-control coded bits which make the information more robust. The maximum data rate of the chip is 50 kbps, and the die area is 3.74 mm(2) using a TSMC 0.18 mu m standard cell library with power consumption 22.49 mW.
VLSI Implementation of a Low Complexity 4x4 MIMO Sphere Decoder with Table Enumeration
(2013)
Yang, Kai-Jiun
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Tsai, Shang-Ho
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Chang, Ruei-Ching
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Chen, Yan-Cheng
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Chuang, Gene C. -H.
In this work a sphere decoder with low complexity is proposed and implemented. We propose a simplified norm algorithm, which is called admissible set elimination (ASE), to dramatically decrease the number of searching nodes. In addition, the decoder uses table- look-up to acquire the enumeration order of different constellations. As a result, the critical path is shortened and the throughput is enhanced. Compared to the optimal ML detector, the proposed scheme greatly improves the complexity and throughput, while the performance only degrades around 0.5 dB. The proposed scheme is fabricated by a TSMC 90 nm process. The area is 0.85 mm(2), and the average throughput can be up to 411.3 Mbps when the clock rate is 108.7 MHz.