Browsing by Author "Yang, Kai-Ming"

Now showing 1 - 9 of 9

Apparent topographic height variations measured by noncontact atomic force microscopy
(2007-07-01)
Yang, Kai-Ming
;
Chung, Jen-Yang
;
Hsieh, Ming-Feng
;
Lin, Deng-Sung
;
物理研究所
The topographic height measurement on a sample consisting of domains of different materials in noncontact atomic force microscopy (NC-AFM) is typically incorrect owing to the variation in electrostatic force between a tip and a sample. The tip-sample electrostatic force is owing to the difference in effective contact potential between a tip and a sample. This study demonstrates that the error in height strongly depends on the bias applied between the tip and the sample, the radius of the tip apex. the work function difference, and the frequency shift. Experimental results are well explained by integrated model calculations and by including the van der Waals and electrostatic forces between the tip and the sample in the analysis. When the simultaneous compensation of contact potentials during imaging is not performed, the errors occurring in the height measurement can be estimated from the tip-sample distance vs the bias curves obtained in situ.
Breakthrough in Cu to Cu Pillar-Concave Bonding on Silicon Substrate with Polymer Layer for Advanced Packaging, 3D, and Heterogeneous Integration
(2017-01-01)
Yang, Yu-Tao
;
Yu, Ting-Yang
;
Kuo, Shu-Chiao
;
Huang, Tai-Yuan
;
Yang, Kai-Ming
In this paper, finite element method (FEM) simulations are carried out with pillar-concave structure using silicon substrate, silicon substrate with polyimide (PI) and with polybenzoxazole (PBO) for realization of Cu-Cu bonding at low temperature. Parameters of bonding temperature, pillar diameter, concave sidewall angle, and multilayer of concave structure are all considered in simulation. In addition, pillarconcave bonding is successfully demonstrated on silicon substrates with bonding temperatures ranging from 60 degrees C to 100 degrees C. Simulation and fabrication results of concept show potential impacts on current semiconductor packaging method with advantages such as high adhesive strength of polymer on various types of substrates, simplified manufacturing process, solder free interconnect and packaging process, Cu-Cu direct bonding at temperature lower than 100 degrees C, and high tolerance in surface roughness.
Growth behaviour of Ge nano-islands on the nanosized Si{111} facets bordering on two {100} planes
(2006-10-28)
Ferng, Shyh-Shin
;
Yang, Tsung-Hsi
;
Luo, Guangli
;
Yang, Kai-Ming
;
Hsieh, Ming-Feng
Si( 100) substrates were used to fabricate various nanosized {111} facets between the ( 100) planes using photolithography and anisotropic wet chemical etching. Following simultaneous Ge chemical vapour deposition on the neighbouring ( 100) and {111} facets, the Ge nano-island formation and distribution was observed on both the ( 100) terraces and the {111} side walls using a dynamical atomic force microscope. The nano-island formation on the nanosized {111} strip facets was found to be strongly suppressed upon reducing the strip width due primarily to the interaction of adatoms on the neighbouring facets. Specifically, the difference in the effective chemical potential of Ge adatoms on the two neighbouring facets leads to the depletion of nano-islands on the {111} strip with width < 500 nm under the growth condition used in this study.
Investigation of Pillar-Concave Structure for Low-Temperature Cu-Cu Direct Bonding in 3-D/2.5-D Heterogeneous Integration
(2020-08-01)
Chou, Tzu-Chieh
;
Yang, Kai-Ming
;
Li, Jian-Chen
;
Yu, Ting-Yang
;
Yang, Yu-Tao
With the advantage of high surface-roughness tolerance, the pillar-concave Cu-Cu direct bonding without chemical-mechanical planarization (CMP) is investigated in detail, including the mechanism of thermal compensation, analysis of roughness, bonding strength, and bonding reliability. With the special design of Cu bond structure, excellent bonding results can be achieved under low thermal budget (150 degrees C for 1 min, atmosphere) with even high roughness of bonding surface. In addition, the pillar-concave scheme applied to fan-out panel-level package (FOPLP) has been demonstrated, showing the high feasibility of this scheme to realize applications in heterogeneous integration.
Low Temperature Cu-Cu Gang Bonding for RDL-First Fan-Out Panel Level Package
(2019-01-01)
Yang, Kai-Ming
;
Chou, Tzu-Chieh
;
Ko, Cheng-Ta
;
Lin, Chen-Hao
;
Chen, Yu-Hua
In this paper, low temperature (190-220 degrees C) Cu-Cu gang bonding at a low vacuum pressure is demonstrated. The low temperature technologies can be applied to the RDL-first Fan-Out panel level package (FOPLP).
Low-Temperature Cu-Cu Direct Bonding Using Pillar-Concave Structure in Advanced 3-D Heterogeneous Integration
(2017-09-01)
Yang, Yu-Tao
;
Chou, Tzu-Chieh
;
Yu, Ting-Yang
;
Chang, Yu-Wei
;
Huang, Tai-Yuan
Low-temperature Cu-Cu bonding utilizing pillar and concave on silicon substrate with and without polymer layer is successfully implemented at 200 degrees C under atmospheric pressure. Finite-element method (FEM) simulations on stress and deformation generated during bonding process are also presented in order to discuss their influence on bonding result of several pillar diameters and of concave sidewall angles originating from the manufacturing process. The alteration of parameters in FEM simulations would also be investigated to enhance the bonding outcome. The parameters include the diameter of pillar, the sidewall angle of concave, the shape of the concave opening, the addition of extra polymer layer under Cu concave layer, the bonding temperature, and the pitch of the pillar-concave structure. The implementation of Cu-Cu bonding using pillar-concave structure could have a prospective effect on existing packaging methods in semiconductor industry with benefits of applicability to various sorts of substrates and low bonding temperature.
Non-Planarization Cu-Cu Direct Bonding and Gang Bonding with Low Temperature and Short Duration in Ambient Atmosphere
(2019-01-01)
Chou, Tzu-Chieh
;
Yang, Kai-Ming
;
Li, Jian-Chen
;
Yu, Ting-Yang
;
Chung, Ying-Ting
Low temperature (150 degrees C) and short duration Cu-Cu direct bonding, without planarization, and gang bonding approaches are demonstrated with excellent bond strength, electrical characteristics, and reliability. The concept is based on the high stress-led inducing deformation and internal friction to achieve low temperature bonding. In addition, the bonding structure has the advantage of high roughness tolerance on surface without CMP requirement. Compared to current products using Cu-Cu direct bonding at 350-400 degrees C with long duration and vacuum requirement, the breakthrough of proposed schemes provides the feasibility for product realization in 3D integration packaging.
Simulation Analysis of Structure Design for Low Temperature Cu-Cu Direct Bonding in Heterogeneous Integration and Advanced Packaging Systems
(2018-01-01)
Pan, Yu-Ming
;
Yang, Yu-Tao
;
Chou, Tzu-Chieh
;
Yu, Ting-Yang
;
Yang, Kai-Ming
In order to realize Cu-Cu bonding at low temperature, Cu pillar-concave structures on silicon substrate and on silicon substrate with another polymer layer, polyimide (PI), are both investigated through simulation. Height of Cu pillar, thickness of upper and lower silicon substrate, and thickness of Cu concave are simulated in this paper. The proposed structure could have great impacts on current semiconductor packaging technology, such as improvement of joint strength, enhancement of adhesive strength between various substrates, a Cu-Cu bonding process lower than 200 degrees C with simplified manufacturing process.
Study on Low Temperature Cu Bonding and Temporary Bond/De-Bond for RDL-First Fan-Out Panel Level Package
(2017-01-01)
Ko, Cheng-Ta
;
Yang, Kai-Ming
;
Lin, Jim-Wein
;
Wang, Chih-Lun
;
Chou, Tzu-Chieh
In this study, Cu-Cu bonding with pillar-concave structure on a polymer layer was investigated to realize better bonding quality at lower temperature, while a low-stress release layer for temporary bond and de-bond by laser ablation was demonstrated to handle a glass panel for re-distribution layer (RDL) process. The low temperature technology can be potentially applied for RDL-first fan-out panel level package (FOPLP).