Browsing by Author "Yang, MJ"

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Effects of low-temperature NH3 treatment on the characteristics of HfO2/SiO2 gate stack
(2005)
Lu, WT
;
Chien, CH
;
Huang, IJ
;
Yang, MJ
;
Lehnen, P
The effects of postdeposition low- temperature (400 degrees C) NH3 treatment (LTN treatment) on the characteristics of the HfO2/ SiO2 gate stack with the TiN gate electrode were studied in this work. After the HfO2 films were deposited using an AIXTRON Tricent atomic vapor deposition system, the LTN treatment was performed prior to the postdeposition annealing (PDA) step to prevent the growth of an additional interfacial layer, which is known to accompany the traditional high- temperature nitridation technique. The effective electrical oxide thickness for the devices annealed at 700 C PDA, either with or without LTN treatment, was estimated to be about 2.2 and 2.3 nm, respectively, without considering quantum effects. It was found that the LTN treatment effectively improves the characteristics of the HfO2/ SiO2 stack gates, such as capacitance- voltage (C-V) characteristics, frequency dispersion, trap generation rate, and dielectric breakdown voltage even at the high PDA temperature of 700 C. (c) 2005 The Electrochemical Society.
Electrical characteristics of thin HfO(2) gate dielectrics prepared using different pre-deposition surface treatments
(2005-01-01)
Chen, CW
;
Chien, CH
;
Perng, TH
;
Yang, MJ
;
Liang, JS
We have investigated the effects that various pre-deposition surface treatments, such as HF dipping (HF-dipped), NH(3) surface nitridation (NH(3)-annealed), and rapid thermal oxidation (RTO-treated), have on the electrical properties of HfO(2) gate dielectrics. The NH(3)-annealed technique is superior to the others because the dielectric subject to NH(3) surface nitridation possesses a tremendously reduced leakage current, the lowest equivalent oxide thickness (EOT),and a moderate, hysteresis width. In contrast, the RTO-treated preparation can only effectively reduce the leakage current by its resultant increased physical thickness and displays considerably severe hysteresis. We have also studied the dependence of hysteresis on the initial inversion bias (V(inv)), temperature, and frequency for-all splits. The hysteresis width increases upon increasing the initial inversion bias and decreasing the temperature, but it is rather insensitive to the measuring frequency. In addition, our experimental results indicate that the hysteresis width depends exponentially on both the initial inversion bias and the temperature, and it can be described well by a general empirical relationship that has the form C(T) (.) exp(R(v)V(inv),). Finally, the conduction currents through the dielectrics are probably dominated by trap-assisted tunneling (TAT) because the current densities display stronger temperature dependence at low voltage than they do at higher voltages. Based on the trap-assisted tunneling model, the corresponding parameters have been extracted and are presented.
Electrical characteristics of thin HfO2 gate dielectrics prepared using different pre-deposition surface treatments
(2005-01-01)
Chen, CW
;
Chien, CH
;
Perng, TH
;
Yang, MJ
;
Liang, JS
We have investigated the effects that various pre-deposition surface treatments, such as HF dipping (HF-dipped), NH3 surface nitridation (NH3-annealed), and rapid thermal oxidation (RTO-treated), have on the electrical properties of HfO2 gate dielectrics. The NH3-annealed technique is superior to the others because the dielectric subject to NH3 surface nitridation possesses a tremendously reduced leakage current, the lowest equivalent oxide thickness (EOT),and a moderate, hysteresis width. In contrast, the RTO-treated preparation can only effectively reduce the leakage current by its resultant increased physical thickness and displays considerably severe hysteresis. We have also studied the dependence of hysteresis on the initial inversion bias (V-inv), temperature, and frequency for-all splits. The hysteresis width increases upon increasing the initial inversion bias and decreasing the temperature, but it is rather insensitive to the measuring frequency. In addition, our experimental results indicate that the hysteresis width depends exponentially on both the initial inversion bias and the temperature, and it can be described well by a general empirical relationship that has the form C(T) (.) exp(RvVinv,). Finally, the conduction currents through the dielectrics are probably dominated by trap-assisted tunneling (TAT) because the current densities display stronger temperature dependence at low voltage than they do at higher voltages. Based on the trap-assisted tunneling model, the corresponding parameters have been extracted and are presented.
Electrical properties of metal-ferroelectric-insulator-semiconductor using sol-gel derived SrBi2Ta2O9 film and ultra-thin Si3N4 buffer layer
(2002-12-02)
Huang, CH
;
Tseng, TY
;
Chien, CH
;
Yang, MJ
;
Leu, CC
The electrical properties of the metal-ferroelectric-insulator-silicon memories with stacked gate configuration of Pt/ SrBi2Ta2O9 (SBT)/Si3N4/p-Si (1 0 0) were investigated. In an attempt to operate at low voltage with sufficient large memory window, various ultra-thin Si3N4 buffer layers in thickness of 3.5, 2, and 0.9 nm were employed. From the results of C-V measurements, the memory window can be as large as 0.8 V at the bias amplitude of 5 V for the sample with 0.9 nm SixNy buffer layer. Well-crystallized perovskite structures have been further confirmed by the spectra of X-ray diffraction measurements. The leakage current, which plays a very important role in the data retention, of Pt/SBT (245 nm)/Si3N4 (0.9 nm)/p-Si (10 0) can be as low as 2.5 X 10(-8) A/cm(2) at 200 kV/cm. Excellent fatigue-free performance with up to 10(10) read/write cycles and good retention time of > 2 h have been obtained. Optimization and scaling of SBT thin films are believed to be effective in pursuing extremely low voltage operation, high-density and liable 1T nonvolatile ferroelectric random access memories. (C) 2002 Elsevier Science B.V. All rights reserved.
HfO2 MIS capacitor with copper gate electrode
(2004-12-01)
Perng, TH
;
Chien, CH
;
Chen, CW
;
Yang, MJ
;
Lehnen, P
Metal-insulator-semiconductor capacitors were fabricated using atomic vapor deposition HfO2 dielectric with sputtered copper (Cu) and aluminum (Al) gate electrodes. The counterparts with SiO2 dielectric were also fabricated for comparison. Bias-temperature stress and charge-to-breakdown (QBD) test were conducted to examine the stability and reliability of these capacitors. In contrast with the high Cu drift rate in an SiO2 dielectric, Cu in contact with HfO2 seems to be very stable. The HfO2 capacitors with a Cu-gate also depict higher capacitance without showing any reliability degradation, compared to the Al-gate counterparts. These results indicate that HfO2 with its considerably high density of 9.68 g/cm(3) is acting as a good barrier to Cu diffusion, and it thus appears feasible to integrate Cu metal with the post-gate-dielectric ultralarge-scale integration manufacturing processes.
High-performance poly-silicon TFTs using HfO2 gate dielectric
(2006-05-01)
Lin, CP
;
Tsui, BY
;
Yang, MJ
;
Huang, RH
;
Chien, CH
High-performance low-temperature poly-Si thin-film transistors (TFTs) using high-kappa (HFO2) gate dielectric is demonstrated for the first time. Because of the high gate capacitance density and thin equivalent-oxide thickness contributed by the high-kappa gate dielectric, excellent device performance can be achieved including high driving current, low subthreshold swing, low threshold voltage, and high ON/OFF current ratio. It should be noted that the O.N-state current of high-kappa. gate-dielectric TFTs is almost five times higher than that of SiO2 gate-dielectric TFTs. Moreover, superior threshold-voltage (V-th) rolloff property is also demonstrated. All of these results suggest that high-kappa gate dielectric is a good choice for high-performance TFTs.
High-performance Pt/SrBi2Ta2O9/HfO2/Si structure for nondestructive readout memory
(2003-09-01)
Chien, CH
;
Wang, DY
;
Yang, MJ
;
Lehnen, P
;
Leu, CC
Metal-ferroelectric-insulator-semiconductor (MFIS) capacitors with 390-nm-thick SrBi2Ta2O9 (SBT) ferroelectric film and 8-nm-thick hafnium. oxide (HfO2) layer on silicon substrate have been fabricated and characterized. It is demonstrated for the first time that the MFIS stack exhibits a large memory window of around 1.08 V at an operation voltage of 3.5 V. Moreover, the MFIS memory structure suffers only 18% degradation in the memory window after 10(9) switching cycles. The excellent performance is attributed to the formation of well-crystallized SBT perovskite thin film on top of the HfO2 buffer layer, as evidenced by the distinctive sharp peaks in X-ray diffraction (XRD) spectra. In addition to its relatively high kappa value, HfO2 also serves as a good seed layer for SBT crystallization, making the proposed Pt/SrBi2Ta2O9/HfO2/Si structure ideally suitable for low-voltage and high-performance ferroelectric memories.
Improvements on electrical characteristics of p-channel metal-oxide-semiconductor field effect transistors with HfO(2) gate stacks by post deposition N(2)O plasma treatment
(2005-11-01)
Lu, WT
;
Chien, CH
;
Lan, WT
;
Lee, TC
;
Yang, MJ
In this work, we found that employing a post deposition N(2)O plasma treatment following the deposition of HfO(2) film can effectively improve the electrical characteristics of p-type channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with a HfO(2) gate stack in terms of lower gate leakage current, lower interface state density, superior subthreshold swing, higher normalized transconductance and enhanced driving current even though it had led to a slightly higher equivalent oxide thickness (EOT) value of the HfO(2) gate stack by around 0.3 nm. In order to clarify the attributes of the improvements, we used charge pumping (CP) measurement to analyze the densities of interface states and bulk traps in the HfO(2) gate stacks. The improvements are then ascribed to the higher interface quality offered by the post deposition N(2)O plasma treatment. Moreover, we found that to more accurately estimate the bulk traps from the CP measurement, the leakage should be taken into account especially at low frequencies. Finally, it was found that the levels of the bulk traps and interface states can be reduced by the N(2)O plasma treatment, which also helps significantly eliminate the degradation of the gate stack during the subsequent voltage stress.
Improvements on electrical characteristics of p-channel metal-oxide-semiconductor field effect transistors with HfO2 gate stacks by post deposition N2O plasma treatment
(2005-11-01)
Lu, WT
;
Chien, CH
;
Lan, WT
;
Lee, TC
;
Yang, MJ
In this work, we found that employing a post deposition N2O plasma treatment following the deposition of HfO2 film can effectively improve the electrical characteristics of p-type channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with a HfO2 gate stack in terms of lower gate leakage current, lower interface state density, superior subthreshold swing, higher normalized transconductance and enhanced driving current even though it had led to a slightly higher equivalent oxide thickness (EOT) value of the HfO2 gate stack by around 0.3 nm. In order to clarify the attributes of the improvements, we used charge pumping (CP) measurement to analyze the densities of interface states and bulk traps in the HfO2 gate stacks. The improvements are then ascribed to the higher interface quality offered by the post deposition N2O plasma treatment. Moreover, we found that to more accurately estimate the bulk traps from the CP measurement, the leakage should be taken into account especially at low frequencies. Finally, it was found that the levels of the bulk traps and interface states can be reduced by the N2O plasma treatment, which also helps significantly eliminate the degradation of the gate stack during the subsequent voltage stress.
Low-temperature growth of polycrystalline ge films on SiO2 substrate by HDPCVD
(2005)
Yang, MJ
;
Shieh, J
;
Hsu, SL
;
Huang, IJ
;
Leu, CC
Pure and high-quality polycrystalline Ge films have been deposited directly onto fully SiO2 covered substrates by high-density plasma chemical vapor deposition (HDPCVD) system. Only a tiny amount of O and C near the surface has been observed from X-ray photoelectron spectroscopy and Auger electron spectroscopy data, which may come from surface oxidation and contamination. Very pure Ge composition has been achieved in the bulk of the films. The cubic structure with primarily (111), (220), and (311) orientations of the Ge films is mainly composed of fine grains and can be unambiguously identified from X-ray diffraction patterns. Furthermore, successful Ge film depositions with nearly no incubation time are demonstrated using a mixture of GeH4/H-2 as process gas at 400 degrees C. Thickness vs. time analysis was performed by high-resolution transmission electron microscopy. The HDPCVD technique used was able to provide a simple, powerful, and reliable approach in the fabrication of polycrystalline Ge thin film transistors. (C) 2005 The Electrochemical Society.
Study of thermal stability of nickel monogermanide on single- and polycrystalline germanium substrates
(2005-06-20)
Hsu, SL
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Chien, CH
;
Yang, MJ
;
Huang, RH
;
Leu, CC
We have investigated the thermal stability of nickel monogermanide (NiGe) films formed by rapid thermal annealing on both single- and polycrystalline Ge substrates. We found that the NiGe phase is the only one present after nickel germanidation in the temperature range 400-700 degrees C. A fairly uniform NiGe film formed on the single-crystalline Ge; it possessed excellent resistivity (15.6 mu Omega cm) and was thermally stable up to 550 degrees C, but it degraded rapidly at higher temperatures as a result of agglomeration. In contrast, the NiGe film formed on the polycrystalline Ge exhibited much poorer thermal stability, possibly because of polycrystalline Ge grain growth, which resulted in columnar NiGe grains interlaced with Ge grains that had a dramatically increased sheet resistance. As a result, we observed that the sheet resistances of NiGe lines subjected to annealing at 500 degrees C depended strongly on the linewidth when this width was comparable with the grain size of the polycrystalline Ge. (c) 2005 American Institute of Physic's.
The characteristics of hole trapping in HfO2/SiO2 gate dielectrics with TiN gate electrode
(2004-10-18)
Lu, WT
;
Lin, PC
;
Huang, TY
;
Chien, CH
;
Yang, MJ
The characteristics of charge trapping during constant voltage stress in an n-type metal-oxide-semiconductor capacitor with HfO2/SiO2 gate stack and TiN gate electrode were studied. We found that the dominant charge trapping mechanism in the high-k gate stack is hole trapping rather than electron trapping. This behavior can be well described by the distributed capture cross-section model. In particular, the flatband voltage shift (DeltaV(fb)) is mainly caused by the trap filling instead of the trap creation [Zafar , J. Appl. Phys. 93, 9298 (2003)]. The dominant hole trapping can be ascribed to a higher probability for hole tunneling from the substrate, compared to electron tunneling from the gate, due to a shorter tunneling path over the barrier for holes due to the work function of the TiN gate electrode. (C) 2004 American Institute of Physics.
The effects of low-pressure rapid thermal post-annealing on the properties of (Ba,Sr)TiO3 thin films deposited by liquid source misted chemical deposition
(2001-12-01)
Yang, MJ
;
Chien, CH
;
Leu, CC
;
Zhang, RJ
;
Wu, SC
The technique of low-pressure post-annealing process with additional second-step annealing for preparation of the Ba0.7Sr0.3TiO3 thin films deposited by liquid source misted chemical deposition (LSMCD) has been proposed. With employing this annealing procedure, the leakage current density can be significantly eliminated by approximately one order of magnitude at 2 V. In particular, process temperature can be reduced from 650 degreesC to 600 degreesC without suffering deteriorated crystallinity issue, which is identified by both C-V measurement and X-ray diffraction spectrum. The extracted dielectric constant is 310 with extreamly low loss tangent of 0.005. The spectrum of atomic force microscopy (AFM) shows that this low-pressure process results in smoother surface topography. Moreover, thermal desorption spectrums assure that less residual organics and contaminations were left after low pressure post-annealing. This may be one of the reasons for lowering crystallization temperature and the improved electrical properties.