Browsing by Author "Yang, SC"

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DiffServ edge routers over network processors: Implementation and evaluation
(2003-07-01)
Lin, YD
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Lin, YN
;
Yang, SC
;
Lin, YS
;
資訊工程學系
Network processors are emerging as a programmable alternative to the traditional ASIC-based solutions in scaling up the data plane processing of network services. This work, rather than proposing new algorithms, illustrates the process of, and examines the performance issues in, prototyping a DiffServ edge router with IXP1200. The external benchmarks reveal that although the system can scale to wire speed of 1.8 Gb/s in simple IP forwarding, the throughput declines to 180-290 Mb/s when. DiffServ is performed due to the double bottlenecks of SRAM and microengines. Through internal benchmarks, the performance bottleneck was found to be able to shift from one place to another en different network services and algorithms. Most of the results reported here should be applicable to other NPs since they have similar architectures and components.
DiffServ over network processors: Implementation and evaluation
(2002)
Lin, YD
;
Lin, YN
;
Yang, SC
;
Lin, YS
;
資訊工程學系
Network processors are emerging as a programmable alternative to the traditional ASIC-based solutions in scaling up the data-plane processing of network services. This work, rather than proposing new algorithms, illustrates the process of and examines the performance issues in, prototyping a DiffServ edge router with IXP1200. The external benchmarks reveal that though the system can scale to wire-speed of 1.8Gbps in simple IP forwarding, the throughput declines to 180Mbpssimilar to290Mbps when DiffServ is performed due to the double bottlenecks of SRAM and microengines. Through internal benchmarks, the performance bottleneck was found to be able to shift from one place to another given different network services and algorithms. Most of the result reported here shall remain the same for other NPs since they have similar architectures and components.
Evaluation on ESD robustness of UPS diode and TFT device by transmission line pulsing (TLP) technique
(2003)
Ker, MD
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Tseng, TK
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Yang, SC
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Shih, A
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Tsai, YM
ESD robustness of Low Temperature Poly-Si (LTPS) diodes and TFT devices has been investigated in this paper. By using the Transmission Line Pulsing (TLP) techniques, the It2 (secondary breakdown current) of LTPS diodes and TFT devices were measured. To evaluate the ESD robustness of components for ESD protection, the shifts of breakdown voltage and cut-in voltage of LTPS diode and TFT devices after TLP stress are considered into failure threshold judgment. From the experimental results, It2 of LTPS diodes under forward-biased stress is better than that of LTPS TFT devices. Furthermore, the It2 of LTPS TFT devices under reverse-biased stress is more robust than it under forward-biased stress. Such investigation results can help us to design a successful ESD protection for the circuits on glass.
Reactive bandwidth arbitration for priority and multicasting control in ATM switching
(1997)
Fang, SJ
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Lin, YS
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Yang, SC
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Shung, CB
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交大名義發表
A new service scheduling scheme, reactive bandwidth arbitration (RBA), is proposed as an effective way to arbitrate the contention among priority classes or between unicast and multicast services in ATM switching. The RBA scheme integrates two previously proposed concepts: bandwidth allocation and reactive arbitration. In, RBA, guaranteed bandwidth is allocated to a connection at call setup based on the traffic characteristics and service requirements, while the arbitration of cell delivery takes into account the queue status to react to traffic fluctuation. Through simulation, we found that by bandwidth allocation, a set of queue threshold levels can be obtained to provide a good approximation to the desired delay performance. Furthermore, around this initial configuration, a linear relationship between the queue threshold and the resulting delay performance car be established to fine-tune the configuration parameters for the desired delay performance. Similar effects were observed as the RBA scheme was applied to arbitrate the contention between unicast and multicast connections in a shared buffer ATM switch. The proposed RBA scheme was incorporated in a queue manager chip for an 8 X 8 shored buffer ATM switch with four priority classes per port and link rate at 622 Mbps. The chip has 130k gates in a chip area of 137.88 mm(2) and operates at 25 MHz.
Test structures to verify ESD robustness of on-glass devices in UPS technology
(2004)
Ker, MD
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Deng, CK
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Yang, SC
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Tasi, YM
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電機學院
Different test structures used to investigate the electrostatic discharge (ESD) robustness of on-glass device in Low Temperature Poly-Si (LTPS) process are proposed in this paper. The transmission line pulse generator (TLPG) is used to monitor the I-V behaviors of on-glass devices in the high-current region, and to evaluate the robustness of those LTPS devices during ESD stress condition. Finally, a successful ESD protection design with P+-i-N+ diodes and a VDD-to-VSS ESD clamp circuit integrated on a LCD panel has been demonstrated with a machine-model (MM) ESD level of up to 275 V, whereas the traditional one only can sustain 100 V MM ESD stress.
VLSI design of a priority arbitrator for shared buffer ATM switches
(1997)
Lin, YS
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Yang, SC
;
Fang, SJ
;
Shung, CB
;
交大名義發表
Priority arbitration is an essential part of the ATM switches in order to support the integration of telecommunication services with difference characteristics. Service priority control selects the connection to output a cell among all connections destined to the same output port. Discard priority control selects the connection to discard a cell when the shared buffer is full. In this paper we present a VLSI design of a priority arbitrator for shared buffer ATM switches. This priority arbitrator is targeted to support our new service priority control scheme, reactive bandwidth arbitration (RBA): and new discard priority control scheme, local pushout discarding (LPD). The priority arbitrator is designed for an 8x8 shared buffer ATM switch with four priority classes per port and a link rate of 622 Mbps. The chip has 130k gates in a chip area of 137.88 mm(2) using 0.6 mu m CMOS technology.