Browsing by Author "Yang, Shang-Hsien"

Now showing 1 - 14 of 14

87% Overall High Efficiency and 11 mu A Ultra-Low Standby Current Derived by Overall Power Management in Laptops With Flexible Voltage Scaling and Dynamic Voltage Scaling Techniques
(2016-04-01)
Yang, Shang-Hsien
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Chiu, Chao-Chang
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Chang, Chih-Wei
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Chen, Chen-Min
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Meng, Che-Hao
The proposed overall power management in laptops can improve overall power conversion efficiency by the flexible voltage scaling (FVS) technique in cooperation with conventional dynamic voltage scaling (DVS) technique. The FVS technique separates the controller into two parts. One is a simple primary side controller and the other is emerged into the power management unit in the laptop for getting direct power control from the microprocessor. 12% light load efficiency and 7% peak efficiency are improved compared to conventional design with the DVS technique only but without the FVS technique. Furthermore, green mode is proposed to effectively reduce chip quiescent current to 11 mu A and to suppress power loss to 10 m W in ultra-light load, which is much smaller than 500 mW standby power defined by the restriction of Energy Star Standard and 40 mW of state-of-art commercial products.
A 100W and 91% GaN-Based Class-E Wireless-Power-Transfer Transmitter with Differential-Impedance-Matching Control for Charging Multiple Devices
(2019-01-01)
Xie, Cheng-Yu
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Yang, Shang-Hsien
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Lu, Shen-Fu
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Lin, Fa-Yi
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Lin, Yen-An
A 20MS/s Buck/Boost Supply Modulator for Envelope Tracking Applications with Direct Digital Interface
(2014)
Yang, Shang-Hsien
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Wey, Chin-Long
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Chen, Ke-Horng
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Lin, Ying-Hsi
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Chen, Jing-Jia
a buck/boost supply modulator (BBSM) is proposed for 4G LTE RF power amplifier (RF-PA) envelope tracking applications. The H-bridges used in non-inverting buck/boost converters are metamorphosed into the current sources and switches of a 4-bit current-steering DAC-like supply modulator. Fast tracking speed is achieved through its inherent open-loop topology, while the direct digital interface provides easy control and integration with digital LTE baseband SoCs. The proposed BBSM is capable of delivering peak power of 2.8W at 20MS/s, with a peak efficiency of 75 %.
A Buck Power Factor Correction Converter with Predictive Quadratic Sinusoidal Current Modulation and Line Voltage Reconstruction
(2016-09)
Yang, Shang-Hsien
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Meng, Che-Hao
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Chiu, Chao-Chang
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Chang, Chih-Wei
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Chen, Ke-Horng
A buck power factor correction (PFC) converter operating in continuous conduction mode (CCM) is influenced by the dead zone, which introduces distortion related to the input line voltage. Such phenomenon limits the maximum power factor (PF) and the minimum total harmonic distortion (THD) achievable. By deriving a methodology to achieve predictive line voltage reconstruction (PLVR), the influence of the dead zone is mitigated. With the prediction of quadratic sinusoidal current modulation ((PSCM)-C-2), the line current is shaped into sinusoid waveform that is in-phase with input line voltage, crucial for. Consequently, the proposed CCM buck PFC can achieve high PF, low THD, and efficiency simultaneously. A test chip was fabricated in 0.5-mu m Bipolar-CMOS-DMOS (BCD) process. The experimental results show a peak PF of 0.95 and a peak efficiency of 98% at 110 Vac.
A CMOS Switched-Capacitor Boost Mode Envelope Tracking Regulator with 4% Efficiency Improvement at 7.7dB PAPR for 20MHz LTE Envelope Tracking RF Power Amplifiers
(2019-01-01)
Kumari, Neha
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Yang, Shang-Hsien
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Chen, Ke-Horng
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Lin, Ying-Hsi
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Lin, Shian-Ru
In this paper, the switched -capacitor boost (SCB) mode envelope tracking (ET) technique with a switched-capacitor circuit and a low dropout (LDO) regulator are used to replace conventional envelope tracking regulators. At a Peak-to-Average Power Ratio (PAPR) of 7.7dB common for LTE communication, the efficiency is 72%, which is 4% higher than the theoretical limit of conventional ET techniques. When PAPR increases from 6.1dB to 7.3dB, the conventional ET efficiency decreases from 82% to 69% whereas the SCB mode increases by 2%.
A Dual-Level Dual-Phase Pulse-Width Modulation Class-D Amplifier with 0.001% THD, 112 dB SNR
(2014-01-01)
Yang, Shang-Hsien
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Yang, Yuan-Han
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Chen, Ke-Horng
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Hung, Chung-Chih
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Wey, Chin-Long
this paper presents a dual-level dual-phase pulse-width modulation (DLDP PWM) Class-D audio amplifier circuit which enhance amplifier linearity and reduce distortion. The proposed DLDP PWM Class-D audio amplifier includes two sets of non-overlapping triangular waves, each at its respectful offset levels. Each set of triangular waves is composed of two 180 degrees out-of-phase triangular waves. The differential power stage consists of 8 power transistors, with voltage swings up to +/- 6V. Simulated results shows that the proposed DLDP PWM Class-D audio amplifier features an SNR up to 105 dB, and the THD is suppressed below 0.001 %, with the 3rd harmonic below -102 dBV.
A Dynamic Bootstrap Voltage Technique for a High-Efficiency Buck Converter in a Universal Serial Bus Power Delivery Device
(2016-04-01)
Chen, Wei-Chung
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Chou, Ying-Wei
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Chien, Meng-Wei
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Chen, Hsin-Chieh
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Yang, Shang-Hsien
The dynamic bootstrap voltage (DBV) technique is proposed to keep high efficiency over wide ranges of load currents for high-power universal serial bus devices. The silicon area of the embedded power management with the DBV technique in the system-on-a-chip can be effectively reduced to 50% of the conventional design with a P-type high-side power MOSFET. Test chips fabricated in 0.25-mu m CMOS process showed a 92% peak efficiency from 1 mA to 1 A. The maximum driving current was higher than 5 A, and the efficiencywas 88%. Compared with the efficiency of the converter without the DBV technique, the efficiency of the converter with DBV technique was improved by about 28%.
A High Efficiency and Fast Transient Digital Low-Dropout Regulator With the Burst Mode Corresponding to the Power-Saving Modes of DC-DC Switching Converters
(2020-04-01)
Lin, Jian-He
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Yang, Shang-Hsien
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Muniandi, Balakumar
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Ma, Yu-Sheng
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Huang, Chia-Ming
The proposed digital low-dropout regulator uses nonlinear switching control (NLSC) technique to suppress voltage ripple to less than 6mV when the switching noise voltage of a switching regulator operating in a power-saving mode is greater than 50mV. In addition, the NLSC technique improves the current efficiency by reducing the quiescent current to less than 10 A and reduces the switching power loss through variable switching frequency control. With a load step of 1-20mA, the transient response time is 1.3 s and the peak current efficiency is 99.8 at heavy loads.
A Low-THD Class-D Audio Amplifier With Dual-Level Dual-Phase Carrier Pulsewidth Modulation
(2015-11-01)
Yang, Shang-Hsien
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Yang, Yuan-Han
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Chen, Ke-Horng
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Lin, Ying-Hsi
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Tsai, Tsung-Yen
In this paper, a class-D audio amplifier which combines the advantages of the phase-shifted carrier pulse-width modulation (PWM) and the multiple-level carrier PWM is proposed with a dual-level dual-phase carrier (DLDPC) PWM. The proposed closed-loop amplifier includes a second-order integrator and a DLDPC triangular wave generator. Two sets of 180. out-of-phase triangular waves are used as carriers, and each set has its respective offset voltage level with nonoverlapping amplitude. By performing the double Fourier analysis, it can be found that the linearity can be enhanced and the distortion can be reduced with the proposed modulation. Experimental results show that the proposed fully differential DLDPC PWM class-D audio amplifier features a total harmonic distortion lower than 0.01% with an output voltage swing of +/- 5 V.
A Single-Inductor Dual-Output Converter with Linear-Amplifier-Driven Cross Regulation for Prioritized Energy-Distribution Control of Envelope-Tracking Supply Modulator
(2017-01-01)
Yang, Shang-Hsien
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Lin, Yen-Ting
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Ma, Yu-Sheng
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Chen, Hung-Wei
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Chen, Ke-Horng
A Temperature Compensated 61-W Class-E Soft-Switching GaN-Based Active Diode Rectifier for Wireless Power Transfer Applications
(2019-01-01)
Yang, Shang-Hsien
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Chen, Ke-Horng
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Lin, Ying-Hsi
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Lin, Shian-Ru
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Tsai, Tsung-Yen
The proposed 6.78-MHz Class-E receiver features a soft-switching and temperature-compensated GaN-based active diode (GAD) rectifier design. Using the temperature dependence of the relationship between the driving voltage and the on-resistance of the switch, the gate-source control voltage of GaN can be adjusted to mitigate efficiency variations based on temperature effects. Moreover, a phase shift comparator activation controller is based on the direct relationship between the phase delay on the gate drive signals and the output power. The temperature dependency voltage offset of the comparator is alleviated with auto-zeroing. GAD rectifier ensures energy transfer up to 61 W and 6.8 A, high efficiency of 92%, and low harmonic distortion of 2.1%.
An Enhanced-Security Buck DC-DC Converter with True-Random-Number-Based Pseudo Hysteresis Controller for Internet-of-Everything (IoE) Devices
(2018-01-01)
Yang, Wen-Hau
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Chu, Li-Cheng
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Yang, Shang-Hsien
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Lai, Yan-Jiun
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Chen, Shao-Qi
An Enhanced-Security Buck DC-DC Converter with True-Random-Number-Based Pseudo Hysteresis Controller for Internet-of-Everything (IoE) Devices
(2018-01-01)
Yang, Wen-Hau
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Chu, Li-Cheng
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Yang, Shang-Hsien
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Lai, Yan-Jiun
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Chen, Shao-Qi
High Accuracy Knee Voltage Detection for Primary-Side Control in Flyback Battery Charger
(2017-04-01)
Yang, Shang-Hsien
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Tsai, Tsung-Hsun
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Chen, Hsin
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Chiu, Chao-Chang
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Chen, Ke-Horng
In a primary-side control flyback charger, the accuracy of a conventional knee voltage detection (KVD) approach to obtain the output voltage is influenced by the inclusion of a snubber circuit. Although the snubber circuit dampens the ringing voltages due to switching, it also affect the resonance frequency which would reduce the timing of the sampling circuit, resulting in the inaccurate sampling of output voltage. By analyzing the snubber circuit and its resonance on the primary side, this paper implements a proposed accuracy knee voltage detection (AKVD) technique to compensate for the induced resonance frequency. Furthermore, the proposed constant current (CC) regulator ensures the accuracy of CC mode by compensating the sensing current error caused by the switching delay of the power transistor. A prototype consisting of a test chip fabricated with a 0.5 mu m BCD process demonstrates a voltage accuracy exceeding 99.63%. This is achieved by mitigating abnormal detections and thus ensuring correct control of charging current throughout the charging period.