Browsing by Author "Yang, Shao-Yu"

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Impacts of Single Trap Induced Random Telegraph Noise on Si and Ge Nanowire FETs, 6T SRAM Cells and Logic Circuits
(2013)
Yang, Shao-Yu
;
Chen, Yin-Nien
;
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Su, Pin
In this paper, we investigate the impacts of single trap induced Random Telegraph Noise (RTN) on the drain current, stability of 6T SRAM cells and logic circuits of Si and Ge NanoWire (NW) FETs. The trap position dependence of the RTN amplitude (Delta Ids/Ids) along the channel length direction is examined. For Si-NW FET, significant RTN impact is observed for trap located near the middle region of channel between the source/drain (worst position), while for Ge-NW FET, the worst position depends on the drain bias (Vds) and gate bias (Vgs). The RTN amplitude of Ge-NW FET exhibits distinctly different Vgs and Vds dependence compared with the Si-NW FET due to lower bandgap, higher permittivity, and band-to-band tunneling at the drain in Ge-NW FET. In particular, it is found that Ge-NW FET may exhibit negative RTN amplitude (Ids increases) with acceptor type trap due to the reduction of band-to-band tunneling length when the trap is located near the drain. Ge-NW FET shows larger Vdd dependence of the RTN amplitude variation. For 6T NW SRAM cell, the READ Static Noise Noise Margin (RSNM) of 64 combinations from trapping/de-trapping state in each cell transistor is examined. The impact of RTN on the leakage of NW inverter is investigated using 3D atomistic TCAD mixed-mode simulations.
Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits
(2014-04-01)
Fan, Ming-Long
;
Yang, Shao-Yu
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
In this paper, we comprehensively review the impacts of single-trap-induced random telegraph noise (RTN) on FinFET, Ge/Si Nanowire FET and Tunnel FET (TFET). The resulting influences on the thermionic-based current conduction such as FinFET, Si-NW FET and Ge-NW FET (at low drain bias) as well as interband tunneling dominated current conduction such as TFET and high-drain-biased Ge-NW FET are extensively addressed in device and circuit level. The location of the trap is shown to have profound impacts and the impacts vary with bias conditions and trap types. The worst-case analysis of the stability/performance and leakage/delay for all possible trapping/detrapping RTN combinations are investigated for FinFET, Si-/Ge-NW FETs and TFET based 6T/8T SRAM cells and logic circuits. (C) 2014 Elsevier Ltd. All rights reserved.