Browsing by Author "Yang, Shyh-Chyi"

Now showing 1 - 3 of 3

A MICRO-WATT MULTI-PORT REGISTER FILE WITH WIDE OPERATING VOLTAGE RANGE
(2009)
Yang, Shyh-Chyi
;
Yang, Hao-I
;
Hwang, Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a micro-watt multi-port register file with wide operating voltage range for micro-power applications is presented. Multibank architecture for simultaneous access with collision detecting technique is proposed. The architecture has been analyzed tinder wide operating voltage range between IV to 0.25V with varies process corner. Negative voltage write scheme ensures successful write in deep sub-threshold region. Also. an improved read buffer footer and controllable pre-charge in read scheme are designed. A 4W/4R 16KB register file is implemented in UMC 90nm CMOS technology. The simulation results show that the maximum active power of multi-port register file can achieve near 22.3-22.9uW at 485 KHz under 0.25V.
Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM
(2011-06-01)
Yang, Hao-I.
;
Yang, Shyh-Chyi
;
Hwang, Wei
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
Negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) weaken PFET and NFET over the lifetime of usage, leading to performance and reliability degradation of nanoscale CMOS SRAM. In addition, most of the state-of-the-art SRAM designs employ replica timing control circuit to mitigate the effects of leakage and process variation, optimize the performance, and reduce power consumption. NBTI and PBTI also degrade the timing control circuits and may render them ineffective. In this paper, we provide comprehensive analyses on the impacts of NBTI and PBTI on a two-port 8T SRAM design, including the stability and Write margin of the cell, Read/Write access paths, and replica timing control circuits. We show, for the first time, that because the Read/Write replica timing control circuits are activated in every Read/Write cycle, they exhibit distinctively different degradation behavior from the normal array access paths, resulting in degradation of timing control and performance. We also discuss degradation tolerant design techniques to mitigate the performance and reliability degradation induced by NBTI/PBTI.
TIMING CONTROL DEGRADATION AND NBTI/PBTI TOLERANT DESIGN FOR WRITE-REPLICA CIRCUIT IN NANOSCALE CMOS SRAM
(2009)
Yang, Shyh-Chyi
;
Yang, Hao-I
;
Chuang, Ching-Te
;
Hwang, Wei
;
電子工程學系及電子研究所
The threshold voltage (V(T)) drifts caused by Negative-Bias temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of nanoscale SRAM over the lifetime of usage. Moreover, most state-of-the-art SRAMs employ replica timing control scheme to mitigate the effects of excessive leakage and variation, and NBTI/PBTI induced V(T) drifts can render the scheme ineffective or even useless. In this paper, we investigate impacts of NBTI and PBTI on SRAM Write operations based on PTM 32nm CMOS technology node poly-gate and high-k metal-gate models. We propose an NBTI/PBTI tolerant Write-replica timing control scheme to mitigate Write margin and performance degradation. By using multi-bank architecture and biasing the virtual supply line of inactive timing-critical circuits to GND to minimize the stress time and maximize the "Recovery" period, the NBTI/PBTI induced SRAM Write performance degradation can be reduced by around 32-48%.