Browsing by Author "Yang, Song-Yu"

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A 2.4 GHz Reference-Less Receiver for 1 Mbps QPSK Demodulation
(2012-03-01)
Chen, Wei-Zen
;
Lu, Tai-You
;
Ou, Wei-Wen
;
Chou, Shun-Tien
;
Yang, Song-Yu
A 2.4 GHz reference-less single chip wireless receiver for 1 Mbps QPSK demodulation is presented. The receiver accomplishes LO carrier recovery and data demodulation directly from the RF received signal without resort to resonator based reference, such as crystal oscillator. Integrating LNA, mixer, LO carrier recovery loop, postamplifier, and digital demodulator on a single chip, the total power consumption is 20.4 mW. The measured phase noise from a recovered carrier at 2.432 GHz is about -111 dBc/Hz at 1 MHz offset. The chip size is 1.75 x 1.55 mm(2).
A 2.4 GHz Reference-less Wireless Receiver for 1Mbps QPSK Demodulation
(2010)
Chen, Wei-Zen
;
Ou, Wei-Wen
;
Lu, Tai-You
;
Chou, Shun-Tien
;
Yang, Song-Yu
A 2.4 GHz reference-less single chip wireless receiver for 1Mbps QPSK demodulation is presented. The receiver accomplishes LO carrier recovery and data demodulation directly from the received RF signal without resort to resonator based reference, such as crystal oscillator. Integrating LNA, mixer, LO carrier recovery loop, post amplifier, and digital demodulator on a single chip, the total power consumption is 20.4mW. The measured phase noise from a recovered carrier at 2.432 GHz is about -112 dBc/Hz at 1 MHz offset. The chip size is 1.75 x 1.55 mm(2).
A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology
(2010-03-01)
Yang, Song-Yu
;
Chen, Wei-Zen
;
Lu, Tai-You
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 10 GHz all digital frequency synthesizer (ADPLL) with dynamic digital loop filter is presented. Governed by a proposed locking process monitor (LPM), the digital loop filter is automatically reconfigured during the frequency acquisition and phase tracking process. The loop bandwidth is also self-adjusted during the locking process so as to achieve fast lock and low noise simultaneously. A skew-compensated phase accumulator is proposed for high speed operation, which preserves the advantages of low power dissipation while eliminating the accumulated timing skew issue. With less than 7 mu s locking time, the measured rms jitter from a 9.92 GHz carrier is about 0.9 ps. The ADPLL core consumes 7.1 mW from a 1 V supply, and the digital I/O cells drains 2.7 mW from a 3.3 V supply for chip measurement. Implemented in a 90 nm CMOS technology, the core area is only 0.352 mm(2).