Browsing by Author "Yang, TH"
Now showing 1 - 20 of 25
- Results Per Page
- Sort Options
Item type:Item, A GeSi-buffer structure for growth of high-quality GaAs epitaxial layers on a Si substrate(2005-01-01) ;Chang, EY ;Yang, TH ;Luo, GL ;Chang, CY材料科學與工程學系A SiGe-buffer structure for growth of high-quality GaAs layers on a Si (100) substrate is proposed. For the growth of this SiGe-buffer structure. a 0.8-mum Si-0.1 Ge-0.9 layer was first grown. Because of the large mismatch between this layer and the Si substrate, many dislocations formed near the interface and in the low part of the Si0.1Ge0.9 layer. A 0.8-mum Si0.05Ge0.95 layer and a 1-mum top Ge layer were subsequently grown. The strained Si0.05Ge0.95/Si0.1Ge0.9 and Ge/Si0.05Ge0.95 interfaces formed can bend and terminate the upward-propagated dislocations very effectively. An in-situ annealing process is also performed for each individual layer. Finally, a 1-3-mum GaAs film was grown by metal-organic chemical vapor deposition (MOCVD) at 600degreesC. The experimental results show that the dislocation density in the top Ge and GaAs layers can be greatly reduced, and the surface was kept very smooth after growth, while the total thickness of the structure was only 5.1 mum (2.6-mum SiGe-buffer structure + 29.5-mum GaAs layer).Item type:Item, A novel method for growing polycrystalline Ge layer by using UHVCVD(2006-02-24) ;Tu, CH ;Chang, TC ;Liu, PT ;Yang, THZan, HWPoly-Ge grown on SiO2 substrates by using one-step ultra-high vacuum chemical vapor deposition (UHVCVD) process with thin Si nucleation layers at very low deposition temperature (350 degrees C) was demonstrated. The results demonstrated that the polycrystalline silicon (poly-Si) nucleation layer is needed for the growth of polycrystalline germanium (poly-Ge) on SiO2 substrates at low growth temperature. SEM image presents the films with uniform rain size and uniform thickness occurring in the samples. The grain size of poly-Ge is about 100 nm. The Raman shift spectrum and XRD spectrum also identified that films are high quality poly-Ge by using this method. (c) 2005 Elsevier B.V. All rights reserved.Item type:Item, A study of boron diffusion from selectively grown epitaxial silicon-germanium into silicon during rapid thermal annealing(2002) ;Yang, TH ;Chang, EY ;Chen, KM ;Chien, CHHuang, HJBoron diffusion from selectively grown epitaxial Si1-xGex into Si during rapid thermal annealing (RTA) was investigated. Selective epitaxial growth (SEG) of in-situ boron-doped strained Si1-xGex epitaxial layers with different Ge percentages were selectively grown by ultra high vacuum chemical molecular epitaxy (UHVCME). The results show that the boron diffusion depth from SEG Si1-xGex into n-type Si depends on boron concentration, Ge profile in the SEG area, and the size of the SEG area. Higher boron concentrations in SEG Si1-xGex film increases the boron diffusion depth. However, the diffusion depth can be reduced by increasing Ge composition in SEG Si1-xGex. It was also found that the samples with graded Ge profiles have higher diffusion depths than those with uniform profiles. In addition, the boron diffusion depth increases with the size of the SEG Si1-xGex area. The strain in SEG Si1-xGex, the chemical potential of Ge in SEG Si1-xGex and the dislocations induced in the SEG Si1-xGex layers are the main reasons for the phenomena observed.Item type:Item, Abundance of mosaic patterns for CNN with spatially variant templates(2002-06-01) ;Hsu, CH ;Yang, TH ;應用數學系Department of Applied MathematicsThis work investigates the complexity of one-dimensional cellular neural network mosaic patterns with spatially variant templates on finite and infinite lattices. Various boundary conditions are considered for finite lattices and the exact number of mosaic patterns is computed precisely. The entropy of mosaic patterns with periodic templates can also be calculated for infinite lattices. Furthermore, we show the abundance of mosaic patterns with respect to template periods and, which differ greatly from cases with spatially invariant templates.Item type:Item, Anisotropic self-diffraction under Bragg mismatching(2001-05-01) ;Wang, B ;Sun, CC ;Yang, TH ;Ye, PChang, JYAnisotropic self-diffraction (ASD) under Bragg mismatch has been studied. We derive a solution that can describe well the diffraction characteristics of the anisotropic self-diffraction under Bragg mismatch. The solution is useful for estimating the Bragg constraint when the ASD is applied to optical information processing. Both the theory and the experiment are presented.Item type:Item, Area-effective FIR filter design for multiplier-less implementation(2003) ;Lin, TJ ;Yang, TH ;Jen, CW ;電子工程學系及電子研究所Department of Electronics Engineering and Institute of ElectronicsThe hardware complexity of digital filters is not controllable by straightforwardly rounding the coefficients to the quantization levels. In this paper, we propose an effective alternative that distributes a pre-defined addition budget to the multiplier-less FIR filters, which takes into account the common sub-expression sharing inside the computations. We successfully integrate a heuristic common sub-expression elimination (CSE) algorithm and the coefficient quantization by successive approximation proposed by Li et al. Besides, we also propose an improved search algorithm for an optimal scale factor to settle the coefficients collectively into the quantization space. Simulation results show that CSE effectively reduces 29.1%similar to31.5% budgets for comparable filter responses. Besides, the improved scale factor exploration helps to find an identical or a better (never worse) quantization result with only 32.67%similar to44.53% run time, whether or not CSE is applied.Item type:Item, Bifurcations and chaos in two-cell cellular neural networks with periodic inputs(2004-09-01) ;Lin, SS ;Lin, WW ;Yang, TH ;應用數學系Department of Applied MathematicsThis study investigates bifurcations and chaos in two-cell Cellular Neural Networks (CNN) with periodic inputs. Without the inputs, the time periodic solutions are obtained for template A = [r, p, s] with p > 1, r > p - 1 and -s > p - 1. The number of periodic solutions can be proven to be no more than two in exterior regions. The input is b sin 2pit/T with period T > 0 and amplitude b > 0. The typical trajectories Gamma(b, T, A) and their omega-limit set omega(b, T, A) vary with b, T and A are also considered. The asymptotic limit cycles A,,(T, A) with period T of Gamma(b, T, A) are obtained as b --> infinity. When T-0 less than or equal to T-0* (given in (67)), Lambda(infinity) and -Lambda(infinity) can be separated. The onset of chaos can be induced by crises of omega(b, T, A) and -omega(b, T, A) for suitable T and b. The ratio A(b) = aT(b)/a(1)(b), of largest amplitude a(1)(b) except for T-mode and amplitude of the T-mode of the Fast Fourier Transform (FFT) of r(b, T, A), can be used to compare the strength of sustained periodic cycle Lambdao(A) and the inputs. When A(b) much less than 1, Lambda(o)(A) dominates and the attractor omega(b, T, A) is either a quasi-periodic or a periodic. Moreover, the range b of the window of periodic cycles constitutes a devil's staircase. When A(b) similar to 1, finitely many chaotic regions and window regions exist and interweave with each other. In each window, the basic periodic cycle can be identified. A sequence of period-doubling is observed to the left of the basic periodic cycle and a quasi-periodic region is observed to the right of it. For large b, the input dominates, omega(b, T, A) becomes simpler, from quasi-periodic to periodic as b increases.Item type:Item, Coefficient optimization for area-effective multiplier-less FIR filters(2003) ;Lin, TJ ;Yang, TH ;Jen, CW ;電子工程學系及電子研究所Department of Electronics Engineering and Institute of ElectronicsThis paper presents the systematic synthesis of multiplier-less FIR filters with a novel complexity-aware quantization algorithm. Both signed-digit representations and common subexpression elimination (CSE) are investigated to reduce the computational complexity at the bit level. For comparable filter responses, the simulation shows that our approach requires only half (49.06%similar to50.94%) additions of the straightforward quantized filters. Both with CSE, our FIR synthesizer has comparable results with the CSD-encoded coefficients, which have the theoretically minimum non-zero terms. Moreover, our approach outperforms CSD in most cases because of the direct control over additions and the zero-overhead insertion of non-zero terms.Item type:Item, Controlled placement of self-organized Ge dots on patterned Si (001) surfaces(2004-02-15) ;Lee, HM ;Yang, TH ;Luo, GL ;Chang, EY材料科學與工程學系The positioning and ordering of the self-organized Ge dots were controlled using the ultra high-vacuum chemical molecular epitaxial growth of Ge on electron beam lithographically patterned Si (001) substrates. The experimental results indicate that the edge smoothness of the etched Si holes affects the distribution and long-range ordering of the Ge dots formed. With optimized etching conditions, the Ge dots can be grown uniformly on the edges of the holes etched on the patterned Si substrates. The sizes of the Ge dots are approximately 10 nm. The proposed, technique can be applied to the fabrication of regimented arrays in signal processing applications.Item type:Item, Dimensionality and Kosterlitz-Thouless transition in single grain Tl-2223 superconducting thin films(1996-04-01) ;Juang, JY ;Lin, HC ;Liu, CK ;Wang, SJYang, THTl2Ba2Ca2Cu3O10+x (Tl-2223) superconducting films with microstructure consisted of submillimeter size grains combining with reactive ion etching technique, has enabled us to investigate the transport properties of this material in a more controllable manner. Both conductivity fluctuations based on the Aslamazov-Larkin theory and the Kosterlitz-Thouless transitions were studied to delineate the two dimensional nature of the material. It was found that, depending on the substrate used, the effective thickness of critical fluctuation and the detailed features of the K-T transition were very different. For films deposited on LaAlO3(100) substrates, the effective thickness of critical fluctuation is about 35 Angstrom compared to a value of 17.5 Angstrom obtained for films deposited on MgO(100) substrate, roughly equal to the c-axis lattice constant and the distance between the trilayer CuO2 planes, respectively. The effective vortex dielectric constant measuring the correlations between vortex pairs near K-T transition were estimated to be 3.0 and 1.6 for films on LaAlO3 and on MgO, repectively. Possible mechanisms based on the defect structures are proposed to account for the observed results.Item type:Item, Efficient strategy for the occasionally proportional feedback method in controlling chaos(1999-05-01) ;Yang, TH ;Chen, SF ;Gou, YS ;電子物理學系光電工程研究所In this work, the generic mechanism of the occasionally proportional feedback (OPF) technique in controlling chaos has been explored extensively. Except for stabilizing the unstable states that are embedded in the chaotic attractors, the OFF method is also found to generate a great number of new states during the control processes. The forms and characteristics of these new states have been addressed. Moreover, we clarify the roles of the parameters in the OFF method and this clarification leads to a practical and systematic approach in adjusting the parameters for control. To demonstrate the validity, an analogous electronic circuit of the resistively shunted Josephson junction oscillator is employed in addition to a numerical illustration of the logistic mapping. [S1063-651X(99)15805-7].Item type:Item, Flower-like distributed self-organized Ge dots on patterned Si (001) substrates(2003-06-15) ;Lee, HM ;Yang, TH ;Luo, GL ;Chang, EY材料科學與工程學系Self-organized Ge dots were obtained utilizing ultra high vacuum chemical molecular epitaxial growth of Ge on electron beam lithographically patterned Si (001) substrates. The dimensions of these etched Si mesa are 65/23/200 nm in diameter/height/period. The sizes and arrangement of the Ge dots were characterized by scanning electron microscopy and atomic force microscopy. The Ge dots have an average base width of 10 nm and the size is quite uniform. Due to the energetically favorable sites, the Ge dots tend to form homocentrically along the Si mesa edge, and their distribution is flower-like. [DOI: 10.1143/JJAP.42.L718].Item type:Item, Growth of high-quality GaAs epitaxial layers on Si substrite by using a novel GeSi buffer strucuture(2004) ;Chang, EY ;Luo, GL ;Yang, TH ;材料科學與工程學系Department of Materials Science and EngineeringA technique to grow high-quality GaAs layers on Si(100) substrate by using a novel SiGe buffer structure is proposed. For the growth of this SiGe buffer structure, a 0.8mum Si0.1Ge0.9,g layer was first grown. Due to the large mismatch between this layer and the Si substrate, many dislocations formed near the interface and in the low part of the Si0.1Ge0.(9) layer. A 0.8mum Si0.05Ge0.95 layer and a 1.0mum top Ge layer were subsequently grown. The Si0.05Ge0.95/Si0.1Ge0.9 and Ge/Si0.05Ge0.95 interfaces formed can bend and terminate the upward-propagated dislocations very effectively. The in situ annealing process is also performed for each individual layer after growth. Finally a 1-3mum GaAs film was grown by MOCVD at 650square. The experimental results show that the dislocation density in the top Ge and GaAs layers can be greatly reduced, and the surface was kept very smooth after growth, while the total thickness of the structure was kept relative thin after the growth (square3.0mum SiGe buffer struture+3.0mum GaAs layer).Item type:Item, Growth of high-quality Ge epitaxial layers on Si(100)(2003-05-15) ;Luo, GL ;Yang, TH ;Chang, EY ;Chang, CYChao, KAA method of growing high-quality epitaxial Ge layers on a Si(100) substrate is reported. In this method, a 0.8 mum Si0.1Ge0.9 layer was first grown. Due to the large lattice mismatch between this layer and the Si substrate, many dislocations form near the interface and in the lower part of the Si0.1Ge0.9 layer. A 0.8 mum Si0.05Ge0.95 layer and a 1.0 mum top Ge layer were subsequently grown on the Si0.1Ge0.9 layer. The formed interfaces of Si0.05Ge0.95/Si0.1Ge0.9 and Ge/Si0.05Ge0.95 can bend and terminate the upward-propagated dislocations very effectively. The in situ annealing process was also performed for each individual layer. Experimental results show that the dislocation density in the top Ge layer can be greatly reduced, and the surface is very smooth, while the total thickness of the structure is only 2.6 mum.Item type:Item, Growth of ZnSe epilayer on Si using Ge/GexSi1-x buffer structure(2004-06-15) ;Yang, TH ;Yang, CS ;Luo, GL ;Chou, WCYang, TYThe epitaxial growth of ZnSe layers on Si substrates utilizing a Ge/Ge0.95Si0.0.5/Ge0.9Si0.1 buffer structure is demonstrated. In this study, we examine the structure, optical characteristics and atomic interdiffusion of the ZnSe epilayer grown on Si. In a sample with a 2degrees off-cut Si substrate, the outdiffusion of Ge into the ZnSe epilayer is suppressed. The low-temperature PL measurements indicate that the sample with a 2degrees off-cut Si substrate improves its optical characteristic effectively. The X-ray diffraction analysis and transmission electron microscopy (TEM) results indicate that the use of a 2degrees off-cut Ge/Ge0.95Si0.05/ Ge0.9Si0.1/Si substrate markedly improves the crystallinity of and reduced the number of threading dislocations in ZnSe grown on Si.Item type:Item, In search of a product mix for semiconductor wafer fabrication facilities by a combined simulation/neural network approach(2001-06-01) ;Yang, TH ;Su, CT ;Feng, YC ;工業工程與管理學系Department of Industrial Engineering and ManagementThe product mix decision has a direct impact on the process tools utilization. While the commonly seen methodologies may be effective in solving the product mix decision problems from many manufacturing settings, they are not adequate in solving the problems from wafer fabrication facilities due to both the complex nature of the wafer fabrication process and the high tool inventory costs. This paper proposes a combined simulation/neural network based approach to solve the product mix problem for a given tool utilization/WIP level. Solution quality of the proposed methodology is justified through a real world case study. Empirical results illustrate its efficiency and effectiveness in solving a product mix problem for semiconductor wafer fabrication facilities. Significance: Product mix decision for wafer fabrication facilities is intrinsically complicated. The realization of a feasible product mix for a given tool utilization/WIP level will facilitate the planning and control of a manufacturing system. It will also have a significant impact to the tool inventory decision.Item type:Item, Interface-blocking mechanism for reduction of threading dislocations in SiGe and Ge epitaxial layers on Si(100) substrates(2004-09-01) ;Yang, TH ;Luo, GL ;Chang, EY ;Hsieh, YCChang, CYA mechanism of interface blocking was proposed to reduce the threading dislocations in the SiGe and Ge layers on Si(100) substrates. In this work, epitaxial Si1-xGex/Si1-(x-y)Gex-y and Ge/SiyGe1-y layers were grown by UHV/CVD. It was surprisingly found that if the variation of the Ge composition, y, across the interface of Si1-xGex/Si1-(x-y)Gex-y or Ge/SiyGe1-y is higher than a certain value, most of the threading dislocations appear to be blocked and confined in the underlying Si1-(x-y)Gex-y or SiGe1-y layer by the interface. It implies that this finding can provide a simple way to grow high-quality relaxed SiGe and Ge layers on the Si substrates. (C) 2004 American Vacuum Society.Item type:Item, Layout design of high-quality SOI varactor(2003) ;Chen, HY ;Chen, KM ;Huang, GW ;Huang, CHYang, THThis paper presents the geometry effect on the characteristics of accumulation type SOI varactor with Mesa-isolation technology. Constant gate area varactors with various geometry condition were implemented to investigate the effects of layout design parameters on overall varactor performance. Physical and mathematic analysis based on the measurement results show that parasitic capacitance at the edge of active region seriously degrads the device quality factor at smallest gate length. The optimized SOI varactor has a quality factor Q of about 150 /GHz/pF at medium gate length varactor. The experiment result can serve as a design reference for high-quality SOI varactors.Item type:Item, Optical characterization of ZnSe epilayers and ZnCdSe/ZnSe quantum wells grown on Ge/Ge0.95Si0.05/Ge0.9Si0.1/Si virtual substrates(2006-03-15) ;Ku, JT ;Kuo, MC ;Shen, JL ;Chiu, KCYang, THSeveral approaches have been employed to grow high-quality ZnSe epilayers on Ge/Ge0.95Si0.05/Ge0.9Si0.1/Si virtual substrates. The ZnSe epilayers were characterized by photoluminescence spectroscopy. Migration enhanced epitaxy and inserting an in situ thermal annealing ZnSe buffer layer effectively reduced the intensity of deep level emissions from the ZnSe epilayer grown on a 6 degrees-tilted Ge/Ge0.95Si0.05/Ge0.9Si0.1/Si virtual substrate. Optimized conditions for growing high-quality ZnSe were used to deposit ZnCdSe/ZnSe multiple quantum wells on Ge/Ge0.95Si0.05/Ge0.9Si0.1/Si virtual substrates. Photoluminescence spectroscopy revealed quantum-confinement effect in the ZnCdSe multiple quantum wells. The evolution of the exciton emission peak energy and the linewidth as a function of temperature indicate a low density of localized sites in the sample with a well width of 1 nm. In the high-temperature regime, the thermal quenching of the excitonic emission intensity from ZnCdSe quantum well structures was governed by the thermal activation of carriers from quantum-well-confined states into barrier states. (c) 2006 American Institute of Physics.Item type:Item, Performance evaluation of ring-structure register file in multimedia applications(2003) ;Lin, TJ ;Chang, CC ;Yang, TH ;Chang, YMLin, CHAs the concurrent functional units in media processors increase continuously to meet the performance needs, the required access (i.e. read or write) ports of the centralized register file (RF) multiply rapidly and cannot be efficiently implemented. We propose a novel ring-structure RF, which is composed of register sub-blocks identical to the RF for a single functional unit. Data exchanges among functional units occur on the switch network of the ring registers. The proposed RF has been integrated into a four-way VLIW DSP processor successfully that demonstrates its effectiveness in DSP kernels. The synthesis result shows that our proposed ring-structure RF saves 91.88% silicon area of the centralized one, while reducing its access time by 77.35%.