Browsing by Author "Yang, Tsung-Yu"

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A highly reliable multi-level and 2-bit/cell operation of wrapped-select-gate (WSG) SONOS memory with optimized ONO thickness
(2007)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
;
Wang, Jer-Chyi
High-performance wrapped-select-gate (WSG) SONOS (silicon-oxide-nitride-silicon) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism with different ONO thickness in WSG-SONOS memory was well investigated. The different programming efficiency of the WSG-SONOS memory with different ONO thickness can be explained by the lateral electrical field extracted from the simulation. Furthermore, multi-level storage is easily obtained and well V-th distribution is also presented. High program/erase speed (10us/5ms) and low programming current (3.5uA) are performed to achieve the multi-level operation with excellent gate and drain disturbance, second-bit effect, data retention and endurance.
Highly reliable multilevel and 2-bit/cell operation of wrapped select gate (WSG) SONOS memory
(2007-03-01)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
;
Wang, Jer-Chyi
In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multilevel and 2-bit/cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mu s/5 ms) and low programming current (3.5 mu A) for our WSG SONOS by a source-side injection. Besides the excellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (> 150 degrees C) and good endurance (> 10(4)) are also presented. This novel WSG-SONOS memory with a multilevel and 2-bit/cell operation can be used in future high-density and high-performance memory application.
Impact of high-k offset spacer in 65-nm node SOI devices
(2007-03-01)
Ma, Ming-Wen
;
Wu, Chien-Hung
;
Yang, Tsung-Yu
;
Kao, Kuo-Hsing
;
Wu, Woei-Cherng
In this letter, 65-nm node silicon-on-insulator devices with high-k, offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-k, offset spacer dielectric can effectively increase the ON-state driving current I-ON and reduce the OFF leakage current I-OFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the I-ON/I-OFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-k offset spacer dielectric.
Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-kappa LTPS-TFT
(2008-02-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Wu, Yi-Hong
In this letter, fluorine ion implantation with low-temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO2 low-temperature poly-Si thin-film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of I-min is achieved because 25% grain-boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO2 gate dielectric and fluorine preimplantation can simultaneously achieve low V-TH similar to 1.32 V, excellent subthreshold swing similar to 0.141 V/dec, and high I-ON/I-min current ratio 1.98 x 10(7).
Impacts of nitric acid oxidation on low-temperature polycrystalline silicon TFTs with high-k gate dielectric
(2007)
Yang, Tsung-Yu
;
Ma, Ming-Wen
;
Kao, Kuo-Hsing
;
Su, Chun-Jung
;
Chao, Tien-Sheng
In this paper, low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFrs) with HfO2 gate dielectric and nitric acid oxidation pre-treatment is investigated. Significant improvement on on/off current ratio and field effect mobility is observed due to the nitric acid oxidation pre-treatment. An excellent on/off current ratio and subthreshold swing, as well as low threshold voltage and I-off can be achieved without any other hydrogen passivation treatments. These improved performances can be attributed to both the high gate capacitance density using high-k gate dielectric and the good interface quality by nitric acid oxidation of poly-silicon.
Improvement on performance and reliability of TaN/HfO2 LTPS-TFTs with fluorine implantation
(2008-03-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Yang, Tsung-Yu
In this paper, we demonstrate the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with TaN metal-gate and HfO2 gate dielectric to achieve high performance characteristics. A high performance LTPS-TFT with low threshold voltage 0.9 V, excellent subthreshold swing 0.15 V/decade and high I-on/I-min current ratio 1.9 x 10(6) are derived without any hydrogen treatment. In addition, we also introduce the fluorine implantation prior to the Si thin-film crystallization to passivate the defects in grain-boundaries of the channel film and HfO2/polysilicon interface. Significant improvements on subthreshold swing and I-min are observed. In addition, the transconductance degradation and threshold voltage instability due to hot carrier stress is also investigated, respectively. Finally, we derive a high reliability and performance LTPS-TFT with low threshold voltage similar to 1.38 V, ultra-low subthreshold swing 0.132 V/decade and high I-on/I-min current ratio 1.21 x 10(7), which is suitable for the application of system-on panel (SOP). (c) 2007 Elsevier Ltd. All rights reserved.
Mobility improvement of HfO2 LTPS-TFTs with nitrogen implanataion
(2007)
Ma, Ming-Wen
;
Yang, Tsung-Yu
;
Kao, Kuo-Hsing
;
Su, Chun-Jung
;
Chao, Tien-Sheng
In this paper, we demonstrate the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFrs) with high-k HfO2 gate dielectric and nitrogen implantation to achieve high-performance characteristics for the first time. Various nitrogen does 5 X 10(13) and 5 X 10(14) cm(-2) were implanted after gate dielectric deposition. Significant improvement 94.4% and 74.4% on transconductance G(m) and field effect mobility, respectively, are observed due to the nitrogen implantation. In addition, a substantial gate leakage current reduction over four orders is also obtained to decrease undesirable power dissipation. Finally, a high performance LTPS-TFT with low subthreshold swing 0.177 V/decade and threshold voltage about 1 V can be achieved without any other hydrogen plasma passivation treatments.
Optimized ONO thickness for multi-level and 2-bit/cell operation for wrapped-select-gate (WSG) SONOS memory
(2008-01-01)
Wu, Woei-Cherng
;
Chao, Tien-Sheng
;
Peng, Wu-Chin
;
Yang, Wen-Luh
;
Chen, Jian-Hao
In this paper, highly reliable wrapped-select-gate (WSG) silicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multi-level and 2-bit/cell operation have been successfully demonstrated. The source-side injection mechanism for WSG-SONOS memory with different ONO thickness was thoroughly investigated. The different programming efficiencies of the WSG-SONOS memory under different ONO thicknesses are explained by the lateral electrical field extracted from the simulation results. Furthermore, multi-level storage is easily obtained, and good V(TH) distribution presented, for the WSG-SONOS memory with optimized ONO thickness. High program/erase speed (10 mu s/5 ms) and low programming current (3.5 mu A) are used to achieve the multi-level operation with tolerable gate and drain disturbance, negligible second-bit effect, excellent data retention and good endurance performance.
Surface Layering and Supersaturation for Top-Down Nanostructural Development during Spin Coating of Polymer/Fullerene Thin Films
(2017-07-19)
Wu, Wei-Ru
;
Su, Chun-Jen
;
Chuang, Wei-Tsung
;
Huang, Yen-Chih
;
Yang, Po-Wei
This study provides new evidence on a long postulated mechanism of phase separation in a polymer/fullerene mixture during spin coating for controlled nanodomains of oriented crystallization and heterojunctions that favor applications in polymer solar cells (PSCs). The simultaneous nanoscale phase separation and crystallization during spin coating of the mixture are traced using in situ grazing-incidence small-and wide-angle X-ray scattering. Combined with the complimentary results from time-resolved optical reflectance spectroscopy, transient stratification of the liquid film during the transition from the flow-to evaporation-dominated stage of spin coating is disclosed; the vertical liquid-liquid phase separation incubates a supersaturated skin layer where fullerene aggregation and polymer crystallization occur and develop concomitantly. Shortly after the transition, the near-surface structural development is largely pinned, leaving the solvent-rich bottom layer to diminish via solvent diffusion and evaporation through the thickened skin layer that finally condenses into the spin-coated film upon solvent depletion. The shear-enhanced surface layering and supersaturation for the surface-down nanostructural development are unexpected in all the existing structural models for PSCs. The mechanistic understanding of coupled vertical phase separation and local nanosegregation provides new insights and alternative strategy to the morphology control of spin-cast PSC active layers in particular and various solution-processed polymeric films in general.