Browsing by Author "Yang, WL"

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Barrier capability of TaNx films deposited by different nitrogen flow rate against Cu diffusion in Cu/TaNx/n(+)-p junction diodes
(2001-01-01)
Yang, WL
;
Wu, WF
;
Liu, DG
;
Wu, CC
;
Ou, KL
This paper investigates the barrier capability of tantalum nitride (TaNx) layers against Cu diffusion. The TaNx layers were reactively sputtered in contact holes to a thickness of 50 nm by using a different nitrogen flow rate. Results indicate that the TaNx layers fail to be a diffusion barrier due to a relative high resistivity for nitrogen flow ratios exceeding 10%. in addition, we found that the phase of alpha -Ta(-N) functions as an effective barrier against Cu diffusion and that Cu/TaN(3-5%)/n(+)-p junction diodes are able to sustain a 30 min furnace anneal up to 500 degreesC without causing degradation of the electrical characteristics. The high-temperature failure of barrier capability for the TaNx layers is due to interdiffusion of Cu and Si across the TaNx film structure to form Cu3Si. The surface roughness and the film structure of TaNx layers determine the ability of Cu and Si interdiffusion. (C) 2001 Elsevier Science Ltd. All rights reserved.
Crystal orientation and nitrogen effects on the carrier mobility of p-type metal oxide semiconductor field effect transistor with ultra thin gate dielectrics
(2006-03-01)
Lee, YJ
;
Ho, PT
;
Yang, WL
;
Chao, TS
;
Huang, TY
In this study, nitrogen dosage effects on p-type metal oxide semiconductor field effect transistors (pMOSFETs) with ultra thin gate dielectric oil Si(100) and Si(111) were investigated. pMOSFETs on Si(111) show a 64% improvement of transconductance over their on Si(100) counterparts. We found that the incorporation of nitrogen enhances the transconductance on Si(100), but degrades that on Si(111). In addition, compared to Si(100), pMOSFETs on Si(111) show a strong dependence with the aspect ratio effect clue to the two-dimensional strain effect.
High quality interpoly dielectrics deposited on the nitrided-polysilicon for nonvolatile memory devices
(2001-07-01)
Yang, WL
;
Chao, TS
;
Cheng, CM
;
Pan, TM
;
Lei, TF
High quality interpoly dielectrics have been fabricated by using NH3 and N2O nitridation on polysilicon and deposition of tetra-ethyl-ortho-silitate (TEOS) oxide with N2O annealing. The surface roughness of polysilicon is improved and the value of weak bonds is reduced due to nitrogen incorporation at the interface, which improves the integrity of interpoly dielectrics, The improvements include a higher barrier height, breakdown strength, and charge-to-breakdown, and a lower leakage current and charge trapping rate than counterparts. It is found that this method can simutaneously improve both charge-to-breakdown (up to 20 C/cm(2)) and electric breakdown field (up to 17 MV/cm).
High quality interpoly-oxynitride grown by NH3 nitridation and N2O RTA treatment
(2001-02-01)
Pan, TM
;
Lei, TF
;
Yang, WL
;
Cheng, CM
;
Chao, TS
In this letter, a method to grow high quality interpolysilicon-oxynitride (interpoly-oxynitride) film is proposed. Samples, nitridized by NH3 with additional N2O annealing and CVD TEOS deposited on poly-oxynitride (poly-I) with RTA NaO oxidation, show excellent electrical properties in terms of very high electric breakdown field, ion; leakage current, high charge to breakdown, and low electron trapping rate. This novel film is a good candidate for an interpoly dielectric of future high density EEPROM and flash memory devices.
Improvement of polysilicon oxide integrity using NF3-annealing
(2000-06-15)
Yang, WL
;
Shieh, MS
;
Chen, YM
;
Chao, TS
;
Liu, DG
We report a method to improve the polysilicon oxide integrity by using NF3-annealing. Incorporating with stronger Si-N and Si-F bonds at the polysilicon/polyoxide interface, significant improvements are found in terms of roughness, breakdown strength, charge-to-breakdown, and stress-induced-leakage-current.
Improving the electrical integrity of Cu-CoSi2 contacted n(+)p junction diodes using nitrogen-incorporated Ta films as a diffusion barrier
(2002-11-01)
Yang, WL
;
Wu, WF
;
You, HC
;
Ou, KL
;
Lei, TF
The study on improving the electrical integrity Of Cu-CoSi2 contacted-junction diodes by using the reactively sputtered TaNx as a diffusion barrier is presented in this paper. In this study, the Cu(300 nm)-CoSi2 (50 nm)/n(+)p junction diodes were intact with respect to metallurgical reaction up to a 350 degreesC thermal annealing while the electrical characteristics started to degrade after annealing at 300 degreesC in N-2 ambient for 30 min. With the addition of a 50-nm-thick TaNx diffusion barrier between Cu and CoSi2, the junction diodes were able to sustain annealing up to 600 degreesC without losing the basic integrity of the device characteristics, and no metallurgical reaction could be observed even after a 750 degreesC annealing in furnace. In addition, the structure of TaNx layers deposited on CoSi2 at various nitrogen flow rates has been investigated. The TaNx film with small grain sizes deposited at nitrogen flow ratios exceeding 10% shows better barrier capability against Cu diffusion than the others.
Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
(1996-11-01)
Lin, HY
;
Chang, CY
;
Lei, TF
;
Liu, FM
;
Yang, WL
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.
Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
(1996-11-01)
Lin, HY
;
Chang, CY
;
Lei, TF
;
Liu, FM
;
Yang, WL
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.
Mobility enhancement of MOSFETs on p-silicon (111) with in situ HF-Vapor. pre-gate oxide cleaning
(2004-09-01)
Chao, TS
;
Lin, YH
;
Yang, WL
;
電子物理學系
;
Department of Electrophysics
In this paper, we grow and characterize in detail native-oxide-free ultrathin gate oxide on silicon (111) by an advance clustered vertical furnace with in situ HF-vapor stripping of the native oxide. Excellent results are demonstrated. Gate oxide integrity is significantly improved in terms of time-to-breakdown, drain current, and transconductance. In-situ HF-vapor cleaning by a clustered vertical furnace appears to be very promising to grow high-quality native-oxide-free gate oxide on silicon (111).
NBTI effects of pMOSFETs with different nitrogen dose imlantation
(2004)
Lee, YJ
;
Tang, LC
;
Wu, MH
;
Chao, TS
;
Ho, PT
NBTI effects with different nitrogen dose implantation and regions were investigated. High nitrogen dose implantation in the channel or source/drain extension results in serious NBTI degradation. Both the dynamic NBTI effects and substrate hot holes effects were also discussed. DNBTI and I-CP were measured simultaneously. Reduction of DeltaV(TH) and I-CP after positive gate bias stressing is related with the recovery of interface states.
Novel cleaning solutions for polysilicon film post chemical mechanical polishing
(2000-07-01)
Pan, TM
;
Lei, TF
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Chen, CC
;
Chao, TS
;
Liaw, MC
Novel cleaning solutions were developed for post-CMP process, surfactant tetra methyl ammonium hydroxide (TMAH) and/or chelating agent ethylene diamine tetra acetic acid (EDTA) were added into the diluted ammonium hydroxide (NH4OH+H2O) alkaline aqueous solution to enhance removal of metallic and organic contamination, From the experimental result, it is found that the particle and metal removal efficiency and the electrical characteristics are significantly improved for post-CMP cleaning.
Reduction of donor-like interface traps of n-type metal-oxide-semiconductor field-effect-transistors using hydrogen-annealed wafer and in-situ HF-vapor treatment
(2006-01-01)
Chao, TS
;
Lin, YH
;
Yang, WL
;
電子物理學系
;
Department of Electrophysics
In this paper, n-type metal-oxide-semiconductor field-effect-transistors (nMOSFETs) of low donor-like interface traps are fabricated on hydrogen-annealed wafers (Hi-wafer) with an in-situ HF-vapor treatment. Gate oxide integrity is significantly improved in terms of drain current, transconductance, and threshold-voltage shift under stressing. We found the improvement is due to the significant reduction of donor-like interface trapping densities. This improvement becomes distinguished when both Hi-wafer and in-situ HF-vapor treatment are utilized.
Retardation in the chemical-mechanical polish of the boron-doped polysilicon and silicon
(2000-05-01)
Yang, WL
;
Cheng, CY
;
Tsai, MS
;
Liu, DG
;
Shieh, MS
;This letter reports on the chemical-mechanical polishing (CMP) of boron doped polysilicon and silicon. Successive polishing was carried out to investigate how the removal rate correlates to the boron concentration as a function of depth in the polysilicon and crystalline silicon. It is found that the removal of baron-doped samples is significantly retarded and strongly correlated with the doping concentration. To the author's knowledge, this work is the first report discussing the retardation effect of boron in the Si-CMP process, This effect is attributed to the activated dopant atoms which are conjectured to inhibit the hydrolysis reaction of Si-Si bonding in the alkaline aqueous solution. In our study, the retardation effect is evident for the boron concentration higher than 5 x 10(18) cm(-3). As a consequence, it may become an issue in CMP process for those layers of selected or complemented doping.
Stability investigation of single-wafer process by using a spin etcher
(2003-07-01)
Kang, TK
;
Wang, CC
;
Tsui, BY
;
Yang, WL
;
Chien, FT
Etch rate instability was found in a spin etcher. When chemical was pumped to the spin etcher, the flow rate became unstable; possibly resulting in a chemical deficiency due to low mass transport at the wafer edge. Consequently, the etch rate and etch uniformity are unstable. The detailed etch mechanism has been investigated and the mass transport deficiency can be avoided. Less than 2% of etch nonuniformity and a stable process can be achieved by achieving a stable flow rate and control of the surface reaction over the whole wafer in spin etching. (C) 2003 The Electrochemical Society.
Suppression of boron penetration by using inductive-coupling-nitrogen-plasma in stacked amorphous/polysilicon gate structure
(1997-06-19)
Yang, WL
;
Lin, CJ
;
Chao, TS
;
Liu, DG
;
Lei, TF
A method is introduced for suppressing the penetration of boron for BF2+-implanted pMOS devices with a stacked amorphous/ poly-Si (SAP) gate structure. It is shown that after inductive-coupling-nitrogen-plasma (ICNP) treatment, boron diffusion through the thin gale oxide is largely suppressed. As shown from the charge-to-breakdown measurements, the ICNP process will improve the quality of pMOS devices, with Q(bd) three times higher than for the control samples.
Suppression of boron penetration in P+-poly-SiGe gate p-channel metal-oxide-semiconductor field-effect transistor using NH3-nitrided and N2O-grown gate oxides
(2004-11-01)
Yang, WL
;
Chao, TS
;
Lai, KH
;
電子物理學系
;
Department of Electrophysics
High-performance p(+)-poly-SiGe-gate p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) have been fabricated using NH3-nitrided or N2O-grown oxide'instead of the conventional O-2-grown oxide. It is found that NH3-nitrided or N2O-grown oxide can suppress boron penetration in the p(+)-poly-SiGe gate, which improves the integrity of gate dielectrics, resulting in a low flat-band voltage shift, subthreshold swing, and drain-induced barrier lowering.