Browsing by Author "Yang, Ya-Wen"

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Fracture prediction of dissimilar thin film materials in Cu/low-k packaging
(2010-08-01)
Lee, Chang-Chun
;
Lee, Chien-Chen
;
Yang, Ya-Wen
;
生物科技學系
;
Department of Biological Science and Technology
For current semiconductor technology, interfacial crack in stacked thin films of Cu/low-k damascene integration is a critical reliability issue that needs to be urgently resolved. In addition to the measurement of 4-point bending test, how to precisely estimate the adhesion energy between dissimilar films through simulation, based on fracture mechanics is important while designing robust interconnect structures as well as developing next-generation low-k materials. Distinct from the former studies, this research proposes a novel tie-release crack prediction technique based on finite element calculations in order to consider the stress-induced impacts on the thermo-mechanical reliability of the microelectronic package with a low-k chip during the different cracking length of film interfaces. To ensure the correctness and feasibility of the presented technique, a plastic ball array (PBGA) package with stacked Cu/low-k interconnects is implemented as test vehicle to validate actual testing data of experiments and evaluate the variation of interfacial cracking energy while silicon chip becomes thinner. Through the combination of J-integral approach with the technique of global-local sub-modeling, all the predicted results for the forgoing referred cases reveal a good agreement with the physical behaviors of devices. Therefore, it can be concluded that the proposed methodology is highly reliable in estimating the occurrence opportunities of interfacial crack.
Lead-free solder joint reliability estimation of flip chip package using FEM-based sensitivity analysis
(2009)
Lee, Chang-Chun
;
Chang, Kuo-Chin
;
Yang, Ya-Wen
;
生物科技學系
;
Department of Biological Science and Technology
Purpose - Integration of Cu/low-k interconnects into the next-generation integrated circuit chips, particularly for devices below the 90 nm technology node, has proved necessary to meet the urgent requirements of reducing RC time delay and low power consumption. Accordingly, establishment of feasible and robust packaging technology solutions in relation to the structural design, as well as material selection of the packaging components, has become increasingly important. Moreover, the nature of low-k materials and the use of lead-free solder greatly increases the complications in terms of ensuring enhanced packaging level reliability. The foregoing urgent issue needs to be quickly resolved while developing various advanced packages. This paper aims to focus on the issues. Design/methodology/approach - The prediction model, especially for the fatigue life of lead-free solder joints, combined with virtual design of experiment with factorial analysis was used to obtain the sensitivity information of selecting geometry/material parameters in the proposed low-k flip-chip (FC) package. Moreover, a three-dimensional non-linear strip finite element model associated with the two levels of specified boundary condition of global-local technique was adopted to shorten the time of numerical calculation, as well as to give a highly accurate solution. Findings - The results of thermal cycling in experimental testing show good agreement with the simulated analysis. in addition, the sensitivity of analysis indicates that the type of underfill material has a significant effect on the lead-free solder joint reliability. Originality/value - A suitable combination of concerned designed factors is suggested in this research to enhance the reliability of low-k FC packaging with Pb-free solder joints.