Browsing by Author "Yang, Yao-Yi"

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A 80V Output Voltage Boost Converter with Low Voltage Ripple for Avalanche Photodiode(APD)
(2011)
Yang, Yao-Yi
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Hsieh, Chun-Yu
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Huang, Tzu-Chi
;
Lee, Yu-Huei
;
Wang, Shih-Wei
The Avalanche Photodiodes (APDs) are widely used in a variety of optical application requiring high sensitivity, such as long-distance optical communication and optical distance measurement, because the APDs can detect the low level light. APDs accompanied with the Transimpedance Amplifier (TIA) are utilized on the receiver side in the communication system. The trend of integrating the active optical components faces the challenge of integrating different voltage levels. In general, the operation voltage of TIA is usually 1.8 V or 3.3 V. However, the APD requires a high reverse-biasing voltage of 40 V - 80 V. Therefore, a high conversation-ratio boost converter must be included to provide the high voltage to bias the APD. Besides, output voltage ripple must be minimized to decrease the influence on communication signals. Experimental results show the 80 V output voltage boosted from the input voltage of 2.5 V. The output voltage ripple is 2 mV under the condition of 1 mA load current.
A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With alpha-Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control
(2012-04-01)
Huang, Tzu-Chi
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Hsieh, Chun-Yu
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Yang, Yao-Yi
;
Lee, Yu-Huei
;
Kang, Yu-Chai
Abattery-free nano-power buck converter with a proposed dynamic on/off time (DOOT) control can achieve high conversion efficiency over a wide load range. The DOOT control can predict the on/off time at different input voltages without a power consuming zero current detection (ZCD) circuit, as well as suppress static power in idle periods. To adapt to the fluctuations in a harvesting system, the proposed alpha-calibration scheme guarantees accurate ZCD over process, voltage variation, and temperature (PVT) in the DOOT to improve power conversion efficiency. Furthermore, the adaptive phase lead (APL) mechanism can improve inherent propagation delay attributable to low-power and non-ideal comparator, thus improving load regulation by a maximum of 30 mV. The test chip was implemented in 0.25-mu m CMOS process with a die area of 0.39 mm(2). Experimental results showed 95% peak efficiency, low static power of 217 nW and good load regulation of 0.1 mV/mA, which are suitable for RF energy harvesting applications.
A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System
(2009)
Lee, Yu-Huei
;
Wang, Shih-Jung
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Yang, Yao-Yi
;
Zheng, Kuo-Lin
;
Chen, Po-Fung
The proposed power management module with 1 V low-voltage PWM controller and dynamic self-biasing mechanism is designed to integrate with ultra-wide band (UWB) system. The on-chip pre-regulator with power conditioning circuit provides a constant and noiseless supply voltage. Instead of using large external compensation circuit, the compensation enhancement multistage amplifier increases system loop gain and stabilizes the system. Moreover, the proposed self-biasing mechanism enhances the power conversion efficiency by 4 % through the handover technique. The fabricated power management module occupies 0.356 mm(2) silicon in 65nm CMOS. With the excellent line/load transient response and the highest efficiency about 93.5%, the proposed power management has the qualification to be integrated in today's system-on-chip (SoC) applications.
A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System
(2010-11-01)
Lee, Yu-Huei
;
Yang, Yao-Yi
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
;
Wang, Shih-Jung
The proposed power management module with a typical 1.2 V low-voltage PWM (LV-PWM) controller and dynamic voltage scaling (DVS) function is designed using 65 nm technology for integration with the ultra-wide band (UWB) system. The on-chip pre-regulator with a power conditioning circuit can provide a regulated supply voltage to the LV-controller. Moreover, the proposed handover technique can achieve the self-biasing mechanism to further reduce power dissipation. To operate in low voltage, the proposed compensation enhancement multistage amplifier (CEMA) can achieve high loop gain and ensure system stability without using any external compensation component. The fabricated power management module occupies 0.356 mm(2) silicon area with an excellent line/load transient response. Owing to the DVS function, the proposed power management can meet the power requirement in the UWB system and other RF transceiver systems.
A High Efficiency and Compact Size 65nm Power Management Module with 1.2V Low-Voltage PWM Controller for UWB System Application
(2009)
Lee, Yu-Huei
;
Wang, Shih-Jung
;
Yang, Yao-Yi
;
Zheng, Kuo-Lin
;
Chen, Po-Fung
This 65 nm power management module with 1.2 V low-voltage PWM controller aims to integrate with ultra-wideband (UWB) system to get high efficiency and compact size. The on-chip pre-regulator with power conditioning circuit provides a constant and noiseless supply voltage. Thus, the voltage variation of battery has less effect on the low-voltage PWM controller. The proposed compensation enhancement multistage amplifier (CEMA) increases system loop gain and stabilizes the system without off-chip compensation circuit. With excellent line/load transient response, the proposed power management has the highest efficiency about 92% and 0.995 mm(2) silicon die area.
A Single-Inductor Bipolar-Output Converter with 5 mV Positive Voltage Ripple for Active Matrix OLED
(2011)
Chen, Wei-Chung
;
Chiu, Chao-Chang
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Hsieh, Chun-Yu
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Huang, Tzu-Chi
;
Lee, Yu-Huei
This paper proposed a single inductor bipolar outputs (SIBO) switching converter for the active matrix Organic Light-Emitting Diode (AMOLED). The negative voltage is generated by the inverting buck-boost converter, which is regulated by the high signal-to-noise ratio comparator. Moreover, the boost converter is utilized to provide the positive output voltage. The proposed switching converter uses the switch sequential to reduce the positive voltage ripple to about 5 mV with the proportional-integral (PI) compensator to guarantee good line and load-regulation. Simulation results show the positive output voltage is regulated to 5V and the negative output voltage is -7V for driving the AMOLED. When the load current is 25 mA and the ESR is 30m Omega, the output voltage ripples are equal to 5 mV and 11 mV for positive and negative voltages, respectively. Besides, the load and line regulations of positive output voltage are 0.24 mV/mA and 5 mV/V, respectively. The maximum efficiency is 88.5% when the input voltage is 4.5 V and the load current is 50mA
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter
(2012-07-01)
Chou, Wen-Shen
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Huang, Tzu-Chi
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Lee, Yu-Huei
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Yang, Yao-Yi
;
Su, Yi-Ping
"This paper proposes a 55 nm CMOS 12-bit current- steering video digital-to-analog converter (DAC) directly powered by the single-inductor dual-output (SIDO) switching converter to compose a dynamic voltage scaling (DVS) system and improve the power efficiency. Dual-DVS control in both digital and analog circuits can effectively reduce power consumption. With various supply voltages, the video DAC can meet several different specifications in the power optimized (PO) mode. Furthermore, for DAC, the proposed 3S method, including finger separating, splitting and shifting, achieves good differential nonlinearity (DNL) performance to 0.78/0.4 least significant bit (LSB) and integral nonlinearity (INL) 1.3/1.0 LSB (with/without SIDO converter) without additional calibration. It also suppresses the switching noise interference from the SIDO converter. Moreover, for SIDO converter, the cross-regulation performance is greatly improved in both transient and steady state to achieve lowest interference for the analog supply. The total power efficiency can be improved up to 11.5% and 28% in the DVS and the PO mode. The SIDO supplied DAC with the dual-DVS function achieves 69.88 dB spurious free dynamic range (SFDR) at the 1 V output swing and 1 MHz input. The proposed intrinsic 12-bit DAC and SIDO converter achieve high definition video DAC performance with the benefit of area and energy efficiency."
An Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters with 91% Peak Efficiency
(2010)
Lee, Yu-Huei
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Chen, Ke-Horng
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Lin, Ying-Hsi
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Yang, Yao-Yi
;
Wang, Shih-Jung
This interleaving energy-conservation mode control for single-inductor dual-output converter uses the superposition technique to yield the optimal average inductor current and 91% peak efficiency. Neither a freewheel stage nor a post-regulator is needed at nominal conditions. The output voltage ripple appears notably minimized over 50% by means of current interleaving at full load. The chip occupies 1.44 mm(2) in 65 nm CMOS and integrates with a 3D architecture for ultra-wide band system.
Current-Mode Synthetic Control (CSC) Technique for High Efficiency DC-DC Boost Converters Over a Wide Load Range
(2011)
Su, Yi-Ping
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Chen, Yi-Chun
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Huang, Han-Hsiang
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Lee, Yu-Huei
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Yang, Yao-Yi
The proposed current-mode synthetic control (CSC) technique in the design of boost converters can improve the transient response time and maintain high conversion efficiency over a wide load range. The CSC technique has high accuracy similar to the current-mode control and doesn't need the slope compensation for simplicity. Besides, the transient response is also improved due to the current-mode hysteresis control. The load-dependent switching frequency at light loads results in high power conversion efficiency. Experimental results show that the output voltage ripple can be kept smaller than 50mV over a wide load current range from 0mA to 400mA with power conversion efficiency higher than 90% at load current of 10mA.
Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters With 91% Peak Efficiency
(2011-04-01)
Lee, Yu-Huei
;
Yang, Yao-Yi
;
Wang, Shih-Jung
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
The proposed single-inductor dual-output (SIDO) converter with interleaving energy-conservation mode (IECM) control is designed using 65 nm technology to power the ultra-wide band (UWB) system. The energy-conservation mode (ECM) control generates four different energy delivery paths for dual buck outputs with only one inductor. In addition, the superposition technique is used to achieve a minimized inductor current level. The average inductor current is equal to the summation of two output loads. Moreover, the IECM control activates the interleaving operation through the current interleaving mechanism to provide large driving capability as well as to reduce the output voltage ripple. As a result, 91% peak efficiency is derived and the output voltage ripple appears notably minimized by 50% using current interleaving at heavy load. The test chip occupies 1.44 mm(2) in 65 nm CMOS and integrates with a three-dimensional (3-D) architecture for inductor integration.
Minimized Transient and Steady-State Cross Regulation in 55-nm CMOS Single-Inductor Dual-Output (SIDO) Step-Down DC-DC Converter
(2011-11-01)
Lee, Yu-Huei
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Huang, Tzu-Chi
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Yang, Yao-Yi
;
Chou, Wen-Shen
;
Chen, Ke-Horng
A single-inductor dual-output (SIDO) step-down DC-DC converter with continuous conduction mode (CCM) operation is proposed to achieve an area-efficient power management module. The low-voltage energy distribution controller (LV-EDC) can simultaneously guarantee good voltage regulation and low output voltage ripple. With the proposed dual-mode energy delivery methodology, cross regulation in steady-state output voltage ripple, which is rarely discussed, and cross regulation in load transient response are both effectively reduced. In addition, the energy mode transition operation helps obtain the appropriate energy operation mode using the energy delivery paths for dual outputs. Moreover, within the allowable output voltage ripple, the automatic energy bypass (AEB) mechanism can reduce the number of energy delivery paths, thereby ensuring voltage regulation and further enhancing efficiency. The test chip, fabricated in 55-nm CMOS, occupies 1.44 mm(2) and achieves 91% peak efficiency, low output voltage ripple, and excellent load transient response for a high-efficiency system-on-a-chip (SoC) integration.
Non-invasion Power Monitoring with 120% Harvesting Energy Improvement by Maximum Power Extracting Control for High Sustainability Power Meter System
(2012)
Huang, Tzu-Chi
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Du, Ming-Jhe
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Yang, Yao-Yi
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Lee, Yu-Huei
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Kang, Yu-Chai
Magnetic energy harvesting (MEH) circuit for system sustainability and power monitoring system with a novel dual-wire current transformer (DWCT) are proposed in this paper. MEH circuit simultaneously senses and harvests the magnetic energy. DWCT has the benefits of non-invasion measurement (NIM) and is easy to use. The designed direct AC-DC rectifier with maximum power extracting (MPE) control fits the characteristic of magnetic energy source. Thus, 120% harvesting power improvement can be achieved under the same sensing current.
Power Management With a Low-Ripple High-Conversion-Ratio 80-V Output Voltage Boost Converter for Avalanche Photodiode System
(2013-07-01)
Yang, Yao-Yi
;
Wang, Shih-Wei
;
Hsieh, Chun-Yu
;
Huang, Tzu-Chi
;
Lee, Yu-Huei
Avalanche photodiodes (APDs) accompanied with the transimpedance amplifiers (TIAs) are often utilized as receivers in the communication system. A drawback of APDs is that the avalanche gain depends on temperature and varies with the bias voltage, leading to a decrease in the quality of communication. Moreover, the bias voltage for a high avalanche gain is up to 80 V, implying that a power module is inevitably required and raises the difficulty of integration. Therefore, a power management is proposed to provide an 80-V voltage and compensates the temperature dependence for a constant avalanche gain. The low-ripple high-conversion-ratio boost converter eliminates the LC resonance resulted from the nonideal effect of diodes to supress the output voltage ripple, implying that a high quality of bias voltage is guaranteed. Experimental results show that the output voltage ripple is 2.12 mV under the condition of 1-mA load current. A 97% accuracy of avalanche gain is proved to guarantee the high quality of APDs.