Browsing by Author "Yang, Yi-Hung"

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A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition
(2014-06-01)
Chen, Wei-Zen
;
Lu, Tai-You
;
Wang, Yan-Ting
;
Jian, Jhong-Ting
;
Yang, Yi-Hung
A 160-GHz frequency-translation PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating a frequency tripler for frequency down conversion. A transformer-based VCO is utilized to alleviate capacitive and resistive load associated with varactor and succeeding buffer stages. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatic frequency sweeping and fast locking. Fabricated in 65 nm CMOS technology, the chip size is 0.92 mm(2). The PLL locking time is less than 3 mu s. This chip drains 24 mW from a 1.2 V power supply.
An 8 Gbps, 4:1 Transition-Aware Self-Toggling Multiplexer
(2014-01-01)
Chen, Wei-Zen
;
Yang, Yi-Hung
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel 8Gbps, 4:1 transition aware multiplexer (MUX) is proposed. The multiplexer core is basically a self-toggling TSPC flip-flop, which is deactivated when no data transition is detected. The high speed serial data is regenerated by gating the triggered clock. It combines the advantages of data retiming to eliminate deterministic jitter. Besides, the short clock-to-Q(b) delay enables high speed multiplexing. Power reduction can be achieved by deactivating the power hungry flip-flop thanks to the random probability of data transition. Fabricated in 55 nm CMOS technology, the core circuit occupies a chip area of 77 x 81 mu m(2) only. It dissipates 10.3 mW from a 1.2 V supply.