Browsing by Author "Yang, Yu-Ming"

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Analog Placement and Global Routing Considering Wiring Symmetry
(2010)
Yang, Yu-Ming
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Jiang, Iris Hui-Ru
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電機學院
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電子工程學系及電子研究所
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College of Electrical and Computer Engineering
Unlike the mature and highly automatic flow for digital layout generation, the existing method to generate an analog layout is far from automatic because it highly depends on the designer\'s expertise. Prior endeavors are mainly dedicated to analog placement because they consider only the device symmetry constraint. This paper raises the wiring symmetry issue to analog layout: wiring symmetry is as crucial as device symmetry. Hence, we propose an analog placement and global routing algorithm to consider both types of symmetry constraints. During placement, we utilize the device folding technique to enhance the flexibility and feasibility on symmetry. Our results show that our algorithm can produce a promising initial layout to speed up the analog design process.
Criticality-Dependency-Aware Timing Characterization and Analysis
(2015)
Yang, Yu-Ming
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Tam, King Ho
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Jiang, Iris Hui-Ru
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
For nanometer design, conventional timing analysis may generate over-optimistic results on criticality-dependent paths. A late arrival time at the data input of a flip-flop lengthens the propagation delay from the clock pin to the data output of this flip-flop, thus degrading the timing margins of paths launching from this flip-flop. To remove the optimism, in this paper, we first propose a simple yet effective triangle model to characterize the criticality-dependency effect. Then, we devise a novel criticality-dependency-aware timing analysis flow, which is seamlessly integrated with the common static timing analysis flow. Experimental results show that our approach can effectively analyze the criticality-dependency effect: Based on the proposed triangle model, we can accurately identify all timing-risky Hip Hops and capture the induced timing margin degradation.
INTEGRA: Fast Multi-Bit Flip-Flop Clustering for Clock Power Saving Based on Interval Graphs
(2011)
Jiang, Iris H. -R.
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Chang, Chih-Long
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Yang, Yu-Ming
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Tsai, Evan Y. -W.
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Chen, Lancer S. -F.
Clock power is the major contributor to dynamic power for modern IC design. A conventional single-bit; flip-flop cell uses an inverter chain with a high drive strength to drive the clock signal. Clustering such cells and forming a multi-bit flip-flop can share the drive strength, dynamic power, and area of the inverter chain, even can save the clock network power and facilitate the skew control. Hence, in this paper, we focus on multi-bit flip-flop clustering at post-placement to gain these benefits. Utilizing the properties of Manhattan distance and coordinate transformation, we model the problem instance by two interval graphs and use a pair of linear-size sequences as our representation. Without enumerating all compatible combinations, we extract only partial sequences that are necessary to cluster flip-flops at a time, thus leading to an efficient clustering scheme. Moreover, our coordinate transformation brings fast; operations to execute our algorithm. Experimental results show the superior efficiency and effectiveness of our algorithm.
INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving
(2012-02-01)
Jiang, Iris Hui-Ru
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Chang, Chih-Long
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Yang, Yu-Ming
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Clock power is the major contributor to dynamic power for modern integrated circuit design. A conventional single-bit flip-flop cell uses an inverter chain with a high drive strength to drive the clock signal. Clustering several such cells and forming a multibit flip-flop can share the drive strength, dynamic power, and area of the inverter chain, and can even save the clock network power and facilitate the skew control. Hence, in this paper, we focus on postplacement multibit flip-flop clustering to gain these benefits. Utilizing the properties of Manhattan distance and coordinate transformation, we model the problem instance by two interval graphs and use a pair of linear-sized sequences as our representation. Without enumerating all possible combinations, we identify only partial sequences that are necessary to cluster flip-flops, thus leading to an efficient clustering scheme. Moreover, our fast coordinate transformation also makes the execution of our algorithm very efficient. The experiments are conducted on industrial circuits. Our results show that concise representation delivers superior efficiency and effectiveness. Even under timing and placement density constraints, clock power saving via multibit flip-flop clustering can still be substantial at postplacement.
iTimerC 2.0: Fast Incremental Timing and CPPR Analysis
(2015-01-01)
Lee, Pei-Yu
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Jiang, Iris Hui-Ru
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Li, Cheng-Ruei
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Chiu, Wei-Lun
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Yang, Yu-Ming
To achieve timing closure, performance-driven optimizations are repeatedly performed throughout the modern IC design flow. Along with these optimization operations, how to incrementally update timing information efficiently and accurately becomes a crucial task for fast turnaround time. On the other hand, to avoid wasteful over-optimization, clock path pessimism should be removed during timing analysis. In order to provide prompt timing information without over-pessimism during iterative optimizations, in this paper, we aim at fast incremental timing and CPPR analysis. We present two delicate techniques, lazy evaluation and lazy propagation, to avoid redundant updates. Our experiments are conducted on the benchmark suite released by TAU 2015 timing analysis contest. Experimental results show that our timer delivers the best results in terms of accuracy, runtime, and memory over all participating teams.
iTimerC: Common Path Pessimism Removal Using Effective Reduction Methods
(2014)
Yang, Yu-Ming
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Chang, Yu-Wei
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Jiang, Iris Hui-Ru
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Static timing analysis is a key process to guarantee timing closure for modern IC designs. Nevertheless, fast growing design complexities and increasing on-chip variations complicate this process. To capture more accurate timing performance of a design, common path pessimism removal is prevalent to eliminate artificially induced pessimism in clock paths during timing analysis. To avoid exhaustive exploration on all paths in a design, in this paper, we present a novel timing analysis framework removing common path pessimism based on block-based static timing analysis, timing graph reduction, and dynamic bounding. Experimental results show that the proposed method is highly scalable, especially with short runtimes for large-scale designs. Moreover, our approach outperforms TAU 2014 timing contest winners, generating accurate results and achieving more than 2.13X speedups.
Novel Pulsed-Latch Replacement Based on Time Borrowing and Spiral Clustering
(2012)
Chang, Chih-Long
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Jiang, Iris Hui-Ru
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Yang, Yu-Ming
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Tsai, Evan Yu-Wen
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Chen, Aki Sheng-Hua
Flip-flops are the most common form of sequencing elements; however, they have a significantly higher sequencing overhead than latches in terms of delay, power, and area. Hence, pulsed-latches are promising to reduce power for high performance circuits. In this paper, we propose a novel pulsed-latch replacement approach to save power and satisfy timing constraints. We fully utilize the intrinsic time borrowing property of pulsed-latches and develop a spiral clustering method with clock gating consideration. In addition, spiral clustering works well for both rectangular and rectilinear shaped layouts; the latter are popular in modern IC design. Experimental results show that our approach can generate very power efficient results.
PushPull: Short-Path Padding for Timing Error Resilient Circuits
(2014-04-01)
Yang, Yu-Ming
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Jiang, Iris Hui-Ru
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Ho, Sung-Ting
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Modern IC designs are exposed to a wide range of dynamic variations. Traditionally, a conservative timing guardband is required to guarantee correct operations under the worst-case variation, thus leading to performance degradation. To remove the guardband, resilient circuits are proposed. However, the short-path padding (hold time fixing) problem in resilient circuits is far severer than conventional IC design. Therefore, in this paper, we focus on the short-path padding problem to enable the timing error detection and correction mechanism of resilient circuits. Unlike recent prior work adopts greedy heuristics with a local view, we determine the padding values and locations with a global view. Moreover, we utilize spare cells and a dummy metal to further achieve the derived padding values at physical implementation. Experimental results show that our method is promising to validate timing error-resilient circuits.