Browsing by Author "Yang, Zhi"

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Circuit and Coil Design for In-Vitro Magnetic Neural Stimulation Systems
(2009-10-01)
Basham, Eric
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Yang, Zhi
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Liu, Wentai
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交大名義發表
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National Chiao Tung University
Magnetic stimulation of neural tissue is an attractive technology because neural excitation may be affected without requiring implantation of electrodes. Pulsed discharge circuits are typically implemented for clinical magnetic stimulation systems. However, pulsed discharge systems can confound in-vitro experimentation. As an alternative to pulsed discharge circuits, we present a circuit to deliver asymmetric current pulses for generation of the magnetic field. We scaled the system down by using ferrite cores for the excitation coil. The scaled system allows observation using electrophysiological techniques and preparations not commonly used for investigation of magnetic stimulation. The design was refined using a comprehensive set of design equations. Circuit modeling and simulation demonstrate that the proposed system is effective for stimulating neural tissue with electric-field gradients generated by time-varying magnetic fields. System performance is verified through electrical test.
NEUSORT2.0: A Multiple-channel Neural Signal Processor with Systolic Array Buffer and Channel-interleaving Processing Schedule
(2008)
Chen, Tung-Chien
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Yang, Zhi
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Liu, Wentai
;
Chen, Liang-Gee
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交大名義發表
An emerging class of neuroprosthetic devices aims to provide aggressive performance by integrating more complicated signal processing hardware into the neural recording: system with a large amount of electrodes. However, the traditional parallel structure duplicating one neural signal processor (NSP) multiple times for multiple channels takes a heavy burden on chip area. The serial structure sequentially switching the processing task between channels requires a bulky memory to store neural data and may has a long processing delay. In this paper, a memory hierarchy of systolic array buffer is proposed to support signal processing interleavingly channel by channel in cycle basis to match up with the data flow of the optimized multiple-channel frontend interface circuitry. The NSP can thus be tightly coupled to the analog frontend interface circuitry and perform signal processing for multiple channels in real time without any bulky memory. Based on our previous one-channel NSP of NFUSORT1.0 [1], the proposed memory hierarchy is realized on NFUSORT2.0 for a 16-channel neural recording system. Compared to 16 of NEUSORT1.0, NEUSORT2.0 demonstrates a 81.50% saving in terms of area x power factor.