Browsing by Author "Yao, Jing-Neng"

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An Au-free GaN High Electron Mobility Transistor with Ti/Al/W Ohmic Metal Structure
(2015)
Yao, Jing-Neng
;
Lin, Yueh-Chin
;
Chuang, Yu-Lin
;
Huang, Yu-Xiang
;
Shih, Wang-Cheng
We demonstrate the Au-free GaN HEMT device with the Ti/Al/W Ohmic metal structure. Excellent surface roughness 4.88nm for Ti/Al/W Ohmic stucture was achieved after metallization. The DC characteristics is comparable with conventional HEMTs and the stress performance with high voltage is better than conventional HEMTs.
Communication-Potential of the pi-Gate InAs HEMTs for High-Speed and Low-Power Logic Applications
(2019-06-07)
Yao, Jing-Neng
;
Lin, Yueh-Chin
;
Wong, Ying-Chieh
;
Huang, Ting-Jui
;
Hsu, Heng-Tung
Composite channel (In0.65Ga0.35As/InAs/In0.65Ga0.35As) high electron mobility transistors (HEMTs) with pi-gate structure were investigated for high-speed and low-power logic applications. The conventional and tri-gate MESA HEMTs were compared with the pi-gate device for evaluation. The pi-gate device exhibited the best maximum transconductance value of 1584 mS/mm, on-state current of 332mA/mm, subthreshold swing (SS) of 78.1 mV/decade, and I-ON/I-OFF ratio of 3 x 10(4) at V-DS = 0.5 V at room temperature. These results indicated that the designed pi-gate InAs devices improve the electrical characteristics of InAs HEMTs for high-speed and low-power logic applications. (c) 2019 The Electrochemical Society.
Effects of layer sequence and postdeposition annealing temperature on performance of La2O3 and HfO2 multilayer composite oxides on In0.53Ga0.47As for MOS capacitor application
(2014-03-01)
Wu, Wen-Hao
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Lin, Yueh-Chin
;
Chuang, Ting-Wei
;
Chen, Yu-Chen
;
Hou, Tzu-Ching
In this paper, we report on high-k composite oxides that are formed by depositing multiple layers of HfO2 and La2O3 on In0.53Ga0.47As for MOS device application. Both multilayer HfO2 (0.8 nm)/La2O3 (0.8 nm)/In0.53Ga0.47As and La2O3 (0.8 nm)/HfO2 (0.8 nm)/In0.53Ga0.47As MOS structures were investigated. The effects of oxide thickness and postdeposition annealing (PDA) temperature on the interface properties of the composite oxide MOS capacitors were studied. It was found that a low CET of 1.41 nm at 1 kHz was achieved using three-layer composite oxides. On the other hand, a small frequency dispersion of 2.8% and an excellent D-It of 7.0 Chi 10(11)cm(-2).eV(-1) can be achieved using multiple layers of La2O3 (0.8 nm) and HfO2 (0.8 nm) on the In0.53Ga0.47As MOS capacitor with optimum thermal treatment and layer thickness. (C) 2014 The Japan Society of Applied Physics
Evaluation of a 100-nm Gate Length E-Mode InAs High Electron Mobility Transistor With Ti/Pt/Au Ohmic Contacts and Mesa Sidewall Channel Etch for High-Speed and Low-Power Logic Applications
(2018-01-01)
Yao, Jing-Neng
;
Lin, Yueh-Chin
;
Hsu, Heng-Tung
;
Yang, Kai-Chun
;
Hsu, Hisang-Hua
In this paper, a 100-nm gate length InAs high electron mobility transistor (HEMT) with non-alloyed Ti/Pt/Au ohmic contacts and mesa sidewall channel etch was investigated for high-speed and low-power logic applications. The device exhibited a low subthreshold swing (SS) of 63.3 mV/decade, a drain induced barrier lowering value of 23.3 mV/V, an I-on/I-off ratio of 1.34 x 10(4), a G(m,max)/SS ratio of 27.6, a current gain cut-off frequency of 439 GHz with a gate delay time of 0.36 ps, and an off-state gate leakage current of less than 1.6 x 10(-5) A/mm at V-DS = 0.5 V. These results demonstrated that the presence of non-annealed ohmic contacts with mesa sidewall etch process allowed the fabrication of InAs HEMTs with excellent electrical characteristics for high-speed and low-power logic applications.
Hydrothermal crystallization and modification of surface hydroxyl groups of anodized TiO2 nanotube-arrays for more efficient photoenergy conversion
(2012-09-01)
Kuo, Yu-Yen
;
Li, Tze-Huei
;
Yao, Jing-Neng
;
Lin, Chiung-Yuan
;
Chien, Chao-Hsin
This paper describes a crystallization method for anodized TiO2 nanotube-array using a hydrothermal process. Pre-sintered TiO2 nanotube-array could further crystallize without experiencing a collapse of the nanotubes under the hydrothermal environment. Applying the hydrothermal crystallization method, the transition of surface bonds of nanotube from Ti-O to Ti-OH/Ti-OH2 can be controlled by acidic hydrothermal pH levels. Dissolution and structural transformation of nanotubes was easily induced if the hydrothermal environment became basic. These effects depicted great influence on the anchoring of carboxylate groups on the surface of TiO2 nanotubes and affected the performance of the dye-sensitized solar cell utilizing the hydrothermally crystallized TiO2 nanotubes as the photoelectrode. The photoenergy conversion efficiency increased from 6.40% for thermally annealed nanotubes to 7.13% for hydrothermally crystallized ones under illumination of 100 rnW cm(-2). (C) 2012 Elsevier Ltd. All rights reserved.
In-x Ga1-x As Materials for Post CMOS Application: Materials and Device Aspects
(2014)
Chang, Edward Yi
;
Lin, Yueh-Chin
;
Luc, Quang-Ho
;
Trinh, Hai-Dang
;
Yao, Jing-Neng
High mobility InxGa1-xAs material is one of the most promising candidates as channel material for post CMOS device applications. In this presentation, InxGa1-xAs material based MOS capacitors will be studied for possible applications for future III-V MOSFET, TFET and FINFET devices. To improve the gate leakage of the InxGa1-xAs MOSCAP, the combination of wet chemical treatment and in-situ trimethyl aluminum (TMA) pretreatment was found to be the most effective method for InxGa1-xAs surface cleaning to achieve a fully inverted InxGa1-xAs MOSCAP for post CMOS digital applications. In addition, a high-k composite oxide composed of La2O3 and HfO2 is investigated for InxGa1-xAs metal-oxide-semiconductor (MOS) capacitor application. The composite oxide was formed by depositing five layers of La2O3(0.8 nm)/HfO2(0.8 nm) on InxGa1-xAs with post deposition annealing at 500 degrees C. The MOS capacitors fabricated show good inversion behavior, high capacitance, low leakage current, with excellent interface trap density (D-it) of 7.0 x 10(11) cm(-2)eV(-1), small hysteresis of 200 mV and low capacitance equivalent thickness of 2.2 nm at 1 kHz were also achieved.