Browsing by Author "Yaung, MF"

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Modeling and formal verification of dataflow graph in system-level design using Petri net
(2005)
Chiang, TH
;
Dung, LR
;
Yaung, MF
;
電控工程研究所
;
Institute of Electrical and Control Engineering
Formal verification in system-level, which also means architecture verification, is different from functional verification in RTL level. DSP algorithms need high-level transformation to achieve optimal goals before mapping on a silicon. However, suitable CAD tool is absent to support the simulation and verification in high-level. This paper presents a novel modeling and high-level verification methodology based on Petri net (PN) model. By proposed method, a system of DSP algorithm in the form of FSFG is transformed into PN model. Moreover, verification methods which include static and dynamical phases are applied in PN domain. At last, we introduce our software implementation, called HiVED, to show the experimental results.