Browsing by Author "Yeh, Chingwei"

Now showing 1 - 3 of 3

Maintaining Color Fidelity for Dual-Shot HDR Imaging
(2014-01-01)
Yeh, Chingwei
;
Tsai, Chen-Yao
;
Lin, Tay-Jyi
;
Guo, Juin-In
;
交大名義發表
HDR synthesis using the minimal number of source images is crucial for real-time applications. This paper identifies the color distortion problem associated with the minimum of two source images, and proposes a solution using the virtual frame composed in the pixel domain. Experimental results demonstrate satisfactory results.
Maintaining Performance on Power Gating of Microprocessor Functional Units by Using a Predictive Pre-Wakeup Strategy
(2011-10-01)
Yeh, Chang-Ching
;
Chang, Kuei-Chung
;
Chen, Tien-Fu
;
Yeh, Chingwei
;
資訊工程學系
Power gating is an effective technique for reducing leakage power in deep submicron CMOS technology. Microarchitectural techniques for power gating of functional units have been developed by detecting suitable idle regions and turning them off to reduce leakage energy consumption; however, wakeup of functional units is needed when instructions are ready for execution such that wakeup overhead is naturally incurred. This study presents time-based power gating with reference pre-wakeup (PGRP), a novel predictive strategy that detects suitable idle periods for power gating and then enables pre-wakeup of needed functional units for avoiding wakeup overhead. The key insight is that most wakeups are repeated due to program locality. Thus, the pre-wakeup predictor learns the wakeup events and selects which prior branch instruction can provide early wakeup (wakeup patterns are visible); these information are then used to adequately prepare available functional units for instruction execution. Simulation results with benchmarks from SPEC2000 applications show that substantial leakage energy reduction with negligible performance degradation (0.38% on average) is worthwhile.
Variable-Length VLIW Encoding for Code Size Reduction in Embedded Processors
(2016-01-01)
Shyu, Ting-Yu
;
Su, Bo-Yu
;
Lin, Tay-Jyi
;
Yeh, Chingwei
;
Wang, Jinn-Shyan
Very-long-instruction-word (VLIW) architectures are widely adopted in high-performance and low-power digital signal processors (DSP) due to their simplicity from extensive software optimizations. However, their poor code density (usually > 2X code size for a given application) and corresponding instruction accesses can overwhelm the energy savings on DSP datapaths. This paper presents variable-length VLIW ((VLIW)-I-2), where the unused condition codes, operands/operand scope, and reduced range of immediate variables of TI C64x+ DSP are exploited to improve the code density. The static grouping and run-time dispersal schemes of the variable-length instructions in a VLIW packet are described. In our experiments, 21% code sizes are saved in average for MiBench kernels. The hardware overhead is only similar to 5%.