Browsing by Author "Yeh, Wen-Kuan"

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3D-TCAD Simulation Study of the Contact All Around T-FinFET Structure for 10nm Metal-Oxide-Semiconductor Field-Effect Transistor
(2016)
Chou, Chen-Han
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Hsu, Chung-Chun
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Yeh, Wen-Kuan
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Chung, Steve S.
;
Chien, Chao-Hsin
We propose a new device structure, namely CAA T-FinFET, for 10nm MOSFETs with using contact all around (CAA) structure. According to 3D simulation study, the CAA T-FinFET possess many advantages over the conventional FinFET structure, such as short channel effect (SCE) suppression by self-aligned oxide (SA oxide), parasitic leakage path isolation with body-tied bulk, sourceldrain series resistance reducing and fin to fin pitch scaling by contact all around process. Base on heterogeneous bulk for strain application, CAA T-FinFET has better electrical performance and easy process control. All these advantages are achieved by depositing a self-aligned oxide after isotropic etching in SID region. Contact all around can efficiently solve the series resistance degradation and pitch scaling by replacing diamond-shape SID stressor with the full contact metal. CAA T-FinFET has high potential to be applied to the varied heterogeneous substrate and high mobility channel (Ge and III-V) MOSFETs by SA oxide.
A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FET
(2016-01-01)
Tang, Ying-Tsan
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Li, Kai-Shin
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Li, Lain-Jong
;
Li, Ming-Yang
;
Lin, Chang-Hsien
An atomic-scale numerical study of Si contact with transition metal dichalcogenides (TMD) semiconductor materials is proposed by first-principles simulation for the first time. The monolayer MoS2 channel can be operated as both of n- and p-type FET by properly doping Si S/D to adjust the TMD channel potential. The gradient MoSx junction of dichalcogenide vacancies enables Si-MoS2 contact resistance lower than 100 Omega-mu m for interface Schottky barrier height reduction. The compact Si-MoS2 interface study can potentially provide monolayer TMD contact design guideline for the sub-5 nm TMD FET fabrication technology.
a-SiGeC Thin Film Photovoltaic Enabled Self-Power Monolithic 3D IC Under Indoor Illumination
(2016)
Kao, Ming-Hsuan
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Yang, Chih-Chao
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Wu, Tsung-Ta
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Hsieh, Tung-Ying
;
Huang, Wen-Hsieh
Low temperature a-SiGeC thin film photovoltaic (TFPV) ambient light-energy harvesters monolithically integrated with high performance 3D sequentially stackable device were demonstrated in this article. The 3D stackable device with threshold voltage engineering and driving current boosting technologies enable excellent current controllability to achieve low I-off and high I-on operation condition for integrated circuit design. The monolithically stacking of Si thin-film energy harvester, which provide output power (21.93uW/cm(2)) under 450 lux indoor illumination, envisions self-power and low cost 3D(+)IC for internet of things.
AlN Surface Passivation of GaN-Based High Electron Mobility Transistors by Plasma-Enhanced Atomic Layer Deposition
(2017-04-27)
Tzou, An-Jye
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Chu, Kuo-Hsiung
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Lin, I-Feng
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Ostreng, Erik
;
Fang, Yung-Sheng
We report a low current collapse GaN-based high electron mobility transistor (HEMT) with an excellent thermal stability at 150 degrees C. The AlN was grown by N-2-based plasma enhanced atomic layer deposition (PEALD) and shown a refractive index of 1.94 at 633 nm of wavelength. Prior to deposit AlN on III-nitrides, the H-2/NH3 plasma pretreatment led to remove the native gallium oxide. The X-ray photoelectron spectroscopy (XPS) spectroscopy confirmed that the native oxide can be effectively decomposed by hydrogen plasma. Following the in situ ALD-AlN passivation, the surface traps can be eliminated and corresponding to a 22.1% of current collapse with quiescent drain bias (V-DSQ) at 40 V. Furthermore, the high temperature measurement exhibited a shift-free threshold voltage (V-th), corresponding to a 40.2% of current collapse at 150 degrees C. The thermal stable HEMT enabled a breakdown voltage (BV) to 687 V at high temperature, promising a good thermal reliability under high power operation.
Comparison of the Physical and Electrical Properties of HfO2/Al2O3/HfO2/GeOx/Ge and HfO2/Al2O3/GeOx/Ge Gate Stacks
(2019-08-01)
Tsai, Yi-He
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Chou, Chen-Han
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Li, Hui-Hsuan
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Yeh, Wen-Kuan
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Lino, Yu-Hsien
A high-quality HfGeOx interfacial layer (IL) was formed in a HfO2/Al2O3/HfO2/GeOx gate stack through thermal annealing. The diffusing of GeO into the HfO2 layer led to the mixing of the GeOx and HfO2 layers, as identified through energy-dispersive X-ray Spectroscopy (EDX). X-ray photo-electron spectroscopy (XPS) data for HfGeOx IL confirmed the formation of Ge-O-Hf bonds owing to the induced shift of the Ge3d(ox) spectra to lower binding energies. The electrical and reliability data indicated that the capacitor with HfGeOx IL presented not only lower interface states density (Dit, approximately 7 x 10(11) eV(-1)cm(-2)) but also less Dit increment (approximately 3 x 10(11) eV(-1)cm(-2)) after stressing than did the capacitor without the HfGeOx IL. Moreover, the Ge p-metal-oxide-semiconductor field-effect transistor HfGeOx IL exhibited a high effective hole mobility (approximately 704 cm(2)/V . s).
Demonstration of HfO2-Based Gate Dielectric With Low Interface State Density and Sub-nm EOT on Ge by Incorporating Ti Into Interfacial Layer
(2019-02-01)
Tsai, Yi-He
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Chou, Chen-Han
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Chung, Yun-Yan
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Yeh, Wen-Kuan
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Lin, Yu-Hsien
HfO2-based gate stacks with titanium (Ti) incorporated into a GeOx interfacial layer (IL) were fabricated on p-Ge substrates. X-ray photoelectron spectroscopy results, incorporating Ti, can efficiently suppress the GeO volatilization. This contributed to achievement of an equivalent oxide thickness of approximately 0.8 nm, a low interface states density D-it of approximately 2.5 x 10(11) eV(-1)cm(-2), and a smaller D-it increment of approximately 1 x 10(11) eV(-1)cm(-2) after constant negative voltage stress at a field of 8 MV/cm. Therefore, Ti is appropriate for improving the quality of GeOx through high temperature annealing.
Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technology
(2015)
Lee, Yao-Jen
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Hou, Fu-Ju
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Chuang, Shang-Shiun
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Hsueh, Fu-Kuo
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Kao, Kuo-Hsing
We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge0.9Si0.1 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl-2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an I-on/I-off ratio exceeding 10(8), the highest ever reported for Ge-based pFETs.
Effect of NH(3) Plasma Nitridation on Hot-Carrier Instability and Low-Frequency Noise in Gd-Doped High-kappa Dielectric nMOSFETs
(2011-03-01)
Chen, Yu-Ting
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Chen, Kun-Ming
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Lin, Cheng-Li
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Yeh, Wen-Kuan
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Huang, Guo-Wei
The effects of post-NH(3) plasma nitridation on device's hot-carrier instability and low-frequency noise in the Hf-based high-kappa/metal-gate n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) with gadolinium (Gd) cap layers are investigated. With postnitridation, the direct-current and 1/f noise characteristics can be improved apparently. Moreover, a hot-carrier stressing-induced threshold voltage shift can be also suppressed despite of a similar transconductance degradation when comparing with that in the device without nitridation. With the charge-pumping and low-frequency noise measurements, we find that the bulk-and interfacial-trap densities can be reduced with nitrogen incorporation. The reduction of bulk and interfacial traps can be contributed to the suppression of Gd diffusion into a high-kappa layer. In this paper, appropriate post-NH(3) plasma nitridation can improve the device performance and reliability and low-frequency noise for a gate-first high-kappa/metal-gate nMOSFET with a Gd cap layer.
Effect of NH3 Plasma Nitridation on Hot-Carrier Instability and Low-Frequency Noise in Gd-Doped High-kappa Dielectric nMOSFETs
(2011-03-01)
Chen, Yu-Ting
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Chen, Kun-Ming
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Lin, Cheng-Li
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Yeh, Wen-Kuan
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Huang, Guo-Wei
The effects of post-NH3 plasma nitridation on device's hot-carrier instability and low-frequency noise in the Hf-based high-kappa/metal-gate n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) with gadolinium (Gd) cap layers are investigated. With postnitridation, the direct-current and 1/f noise characteristics can be improved apparently. Moreover, a hot-carrier stressing-induced threshold voltage shift can be also suppressed despite of a similar transconductance degradation when comparing with that in the device without nitridation. With the charge-pumping and low-frequency noise measurements, we find that the bulk-and interfacial-trap densities can be reduced with nitrogen incorporation. The reduction of bulk and interfacial traps can be contributed to the suppression of Gd diffusion into a high-kappa layer. In this paper, appropriate post-NH3 plasma nitridation can improve the device performance and reliability and low-frequency noise for a gate-first high-kappa/metal-gate nMOSFET with a Gd cap layer.
Enabling n-type polycrystalline Ge junctionless FinFET of low thermal budget by in situ doping of channel and visible pulsed laser annealing
(2017-02)
Huang, Wen-Hsien
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Shieh, Jia-Min
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Kao, Ming-Hsuan
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Shen, Chang-Hong
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Huang, Tzu-En
A low-thermal-budget n-type polycrystalline Ge (poly-Ge) channel that was prepared by plasma in-situ-doped nanocrystalline Ge (nc-Ge) and visible pulsed laser annealing exhibits a high electrically active concentration of 2 x 10(19) cm(-3) and a narrow Raman FWHM of 3.9 cm(-1). Furthermore, the fabricated n-type poly-Ge junctionless FinFET (JL-FinFET) shows an I-on/I-off ratio of 6 x 10(4), V-th of % -0.3 V, and a subthreshold swing of 237mV/dec at V-d of 1V and DIBL of 101mV/V. The poly-Ge JL-FinFET with a high-aspect-ratio fin channel is less sensitive to V-th roll-off and subthreshold-swing degradation as the gate length is scaled down to 50 nm. This low-thermal-budget JL-FinFET can be integrated into three-dimensional sequential-layer integration and flexible electronics. (C) 2017 The Japan Society of Applied Physics
Experimental Realization of Thermal Stability Enhancement of Nickel Germanide Alloy by Using TiN Metal Capping
(2017-05-01)
Chou, Chen-Han
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Tsai, Yi-He
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Hsu, Chung-Chun
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Jau, Yu-Hau
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Lin, Yu-Hsien
In this paper, we demonstrated the enhancement of thermal stability of nickel germanide (NiGe) alloy up to 600 degrees C by using titanium nitride (TiN) metal capping. A high ION/IOFF ratio of 2.9 x 105 was achieved by capping TiN metal on Ni for NiGe alloy formation at 600 degrees C. Detailed analyses were performed for realizing the mechanism for TiN capping on NiGe/Ge, including vertical element diffusion profile observation through depth-profiling X-ray photoelectron spectroscopy (XPS), element diffusion distribution by energy-dispersive X-ray spectroscopy mapping, and direct junction leakage current path detection by conductive atomic force microscopy. The experimental results indicated that TiN capping can reduce the risk of agglomeration and form a graded NiGe/Ge Schottky junction that is beneficial for suppressing the degradation of junction leakage. Subsequently, we compared the electrical performance of TiN/NiGe/n-Ge at various N/Ti ratios of TiNs. Based on the depth-profiling XPS results and electrical performance, TiN with an N/Ti ratio of approximately 1: 1 can resist the Ni and Ge diffusion, which facilitates the suppression of the agglomeration process. However, the TiN capping layers with an N/Ti ratio of less than approximately 1:1 (Ti-rich) were not favorable for resisting Ni and Ge diffusion.
Experimental Verification of RF Stress Effect on Cascode Class-E PA Performance and Reliability
(2012-06-01)
Yuan, Jiann-Shiun
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Yen, Hsuan-Der
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Chen, Shuyu
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Wang, Ruey-Lue
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Huang, Guo-Wei
A cascode class-E power amplifier (PA) operating at 5.2 GHz has been designed using Advanced Design System simulation. RF circuit performances such as output power and power-added efficiency before and after RF stress have been experimentally investigated. The measured output power, power-added efficiency, and linearity after high-input-power RF stress at elevated supply voltage show significant circuit degradations. The impact of hot-carrier injection and gate oxide soft breakdown on cascode class-E PA reliability is discussed.
First Experimental Demonstration and Mechanism of Abnormal Palladium Diffusion Induced by Excess Interstitial Ge
(2018-11-01)
Chou, Chen-Han
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Shih, An-Shih
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Yu, Shao-Cheng
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Lin, Yu-Hsi
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Tsai, Yi-He
This letter represents the first direct experimental demonstrations and mechanism proposal regarding abnormal palladium diffusion into germanium (Ge). Our experiments indicated that excess Ge atoms among palladium germanide alloy formation indirectly induce the abnormal out-diffusion of mass palladium atoms into Ge. Consequently, palladium germanide alloy on both n-type and p-type Ge form ohmic-like Schottky junctions. To identify this phenomenon, first-principle calculations and technology computer-aided design simulation were used to evaluate the electrical influence of palladium atoms in Ge. We discovered that the activated palladium atoms in Ge induce large midgap bulk-trap states, which contribute to a severe increment of trap-assisted tunneling current at the palladium germanide/Ge junction.
First Fully Functionalized Monolithic 3D(+) IoT Chip with 0.5 V Light-electricity Power Management, 6.8 GHz Wireless-communication VCO, and 4-layer Vertical ReRAM
(2016-01-01)
Hsueh, Fu-Kuo
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Shen, Chang-Hong
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Shieh, Jia-Min
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Li, Kai-Shin
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Chen, Hsiu-Chih
For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D(+)-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D(+) UTB-MOSFETs (600 mu A/282 mu A@V-G = +/- 1V for 10-channel P/N FETs) was fabricated by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO2 far-infrared laser annealing (CO2-FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset <1.2V/1.8V, 3-bits/cell). This unique TSV-free monolithic 3D(+)IC process provides the superiority in 3D hetero-integration; we successfully integrate these circuits in a low cost, small footprint, fully functionalized 3D(+) IoT chip.
High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications
(2015)
Lee, Yao-Jen
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Cho, Ta-Chun
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Sung, Po-Jung
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Kao, Kuo-Hsing
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Hsueh, Fu-Kuo
A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth (< 5nm) and an abrupt steepness (< 0.8 nm/dec). The dopant activation of the devices experienced MLD and MWA is further enhanced by the nonmelting COLSA without dopant diffusion, and which can also avoid fin deformation and recover surface defects left by fin patterning. Thanks to the enhanced dopant activation by COLSA, the SDP-FinTFTs overall exhibit better performance than the SDP-FinTFTs without COLSA and the conventional implanted (imp) FinTFTs in terms of subthreshold swing (S.S.), on-currents (I-on by 160% compared to the SDP-FinTFTs without COLSA) and on/off current ratio (I-on/I-off > 10(7)) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.
Hybrid Si/TMD 2D Electronic Double Channels Fabricated Using Solid CVD Few-Layer-MoS2 Stacking for V-th Matching and CMOS-Compatible 3DFETs
(2014)
Chen, Min-Cheng
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Lin, Chia-Yi
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Li, Kai-Hsin
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Li, Lain-Jong
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Chen, Chang-Hsiao
Stackable 3DFETs such as FinFET using hybrid Si/MoS 2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) I-on,I-n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device V-th are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics.
Improving Thermal Stability and Interface State Density of High-kappa Stacks by Incorporating Hf into an Interfacial Layer on p-Germanium
(2016-11)
Tsai, Yi-He
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Chou, Chen-Han
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Shih, An-Shih
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Jau, Yu-Hau
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Yeh, Wen-Kuan
We propose a new HfGeOx interfacial layer (IL) for the high-kappa gate-stacks on p-type germanium substrate with improved thermal stability as compared with that of conventional GeOx IL. We inserted an additional HfO2 layer after the formation of GeOx in the HfO2/Al2O3/GeOx/Ge gate-stack by using plasma-enhanced atomic layer deposition. Through the use of post-deposition annealing and post-metal annealing, the new system exhibited greater thermal immunity and was stable up to 600 degrees C. We speculate that the improvement originates from the formation of HfGeOx through the combination of HfO2 and GeOx, according to the thermodynamic data. By incorporating Hf into interfacial layer, the fabricated high-kappa gate-stack with an equivalent oxide thickness of 1.2 nm, a low interface states density (D-it) of approximately 3.3 x 10(11) eV(-1) cm(-2), and an impressive gate leakage current of approximately 2.2 x 10(-6) A/cm(2) at VFB-1V.
Incorporating Yttrium into a GeO Interfacial Layer with HfO2-Based Gate Stack on Ge
(2018-01-01)
Chou, Chen-Han
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Lu, Yu-Hong
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Tsai, Yi-He
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Shih, An-Shih
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Yeh, Wen-Kuan
In this study, we employed the electrical and material properties of various interfacial layers (ILs) such as GeO and YGeO on a Ge substrate. First, capacitors using various ILs with HfO2-based gate stacks were developed. The capacitor using YGeO IL exhibited a low interface state density (D-it) of 2.5 x 10(11) eV(-1)cm(-2) and an equivalent oxide thickness of 1.8 nm. Next, a reliability test for constant voltage stress was conducted for further studying the YGeO ILs. The capacitors with YGeO ILs presented higher immunity for Dit degradation. Further, to understand the material properties of various ILs, a simple experiment on capping a Si chip on GeO or YGeO/Ge samples through high-temperature annealing was conducted. We observed that Ge and GeO vapors can be absorbed by Si and detected through X-ray photoelectron spectroscopy (XPS). XPS spectra of Si chips capped on GeO IL presented obvious features of Ge and GeO through annealing at 500 degrees C; however, the XPS spectra of Si chips capped on YGeO IL presented no features, indicating that YGeO ILs had higher thermal stability than GeO ILs. To further analyze the HfO2-based gate stacks with various ILs, Ge diffusion into a high-k HfO2 layer was investigated through angle-resolved XPS. We observed that YGeO ILs with HfO2-based gate stacks can reduce Ge diffusion into a HfO2 layer. (C) 2018 The Electrochemical Society.
Junction-less poly-Ge FinFET and charge-trap NVM fabricated by laser-enabled low thermal budget processes
(2016-06-13)
Huang, Wen-Hsien
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Shieh, Jia-Min
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Shen, Chang-Hong
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Huang, Tzu-En
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Wang, Hsing-Hsiang
A doping-free poly-Ge film as channel material was implemented by CVD-deposited nano-crystalline Ge and visible-light laser crystallization, which behaves as a p-type semiconductor, exhibiting holes concentration of 1.8 x 10(18) cm(-3) and high crystallinity (Raman FWHM similar to 4.54 cm(-1)). The fabricated junctionless 7 nm-poly-Ge FinFET performs at an I-on/I-off ratio over 10(5) and drain-induced barrier lowering of 168mV/ V. Moreover, the fast programming speed of 100 mu s-1 ms and reliable retention can be obtained from the junctionless poly-Ge nonvolatile-memory. Such junctionless poly-Ge devices with low thermal budget are compatible with the conventional CMOS technology and are favorable for 3D sequential-layer integration and flexible electronics. Published by AIP Publishing.
Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits
(2018-01-01)
Yang, Chih-Chao
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Hsieh, Tung-Ying
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Huang, Po-Tsang
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Chen, Kuan-Neng
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Wu, Wan-Chi
A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO2. The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing (<70mV/doc.), high driving currents (n-type: 363 mu A/mu m and p-type: 385 mu A/mu m), and high I-on/I-off(>10(6)). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 degrees C.