Browsing by Author "Yeh, YH"

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Buffer size optimization for full-search block matching algorithms
(1997)
Yeh, YH
;
Lee, CY
;
交大名義發表
;
電子工程學系及電子研究所
;
National Chiao Tung University
This paper presents how to find optimized buffer size for VLSI architectures of full-search block matching algorithms. Starting from the DG (dependency graph) analysis, we focus in the problem of reducing the internal buffer size under minimal I/O bandwidth constraint As a result a systematic design procedure for buffer optimization is derived to reduce realization cost.
Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms
(1999-09-01)
Yeh, YH
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents two efficient very large scale integration (VLSI) architectures and buffer size optimization for full-search block matching algorithms. Starting from an overlapped data how of search area, both systolic- and semisystolic-array architectural solutions are derived. By means of exploiting stream memory banks, not only input/output (I/O) bandwidth can be minimized, but also processor element efficiency can be improved, In addition, the controller structure for both solutions are very straightforward, making them very suitable for VLSI implementation to meet computational requirements. Moreover, by exploring the dependency graph, we focus on the problem of reducing the internal buffer size under minimal I/O bandwidth constraint to derive guidelines on reducing redundant internal buffer as well as to achieve area-efficient VLSI architectures. Simulation results show that, for N = P = 16 (N is the reference block size and P is the search range), I/O bandwidth can be reduced by 2.4 times, while buffer size increases less than 38%. Two prototype chips for N = P = 16 have been designed and fabricated. Test results show that clock rate can be up to 90 MHz, implying that more than 87.9-K motion vectors per second can be achieved to meet real-time requirements specified in MPEG-2 MP@ML coding standard.
Efficient channel estimation based on discrete cosine transform
(2003)
Yeh, YH
;
Chen, SG
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Channel impairment caused by multi-path reflections can deeply degrade the transmission efficiency in wireless communication systems. Based on the property of the channel frequency response and the concept of interpolation, in this paper a DCT-based pilot-aided channel estimator for orthogonal frequency division multiplexing is proposed. This approach can mitigate the aliasing effect in the DFT-based channel estimator when there is nonsample-spaced path delay. Compared with DFT-based estimator, DCT-based estimator significantly improves the performance with a comparable complexity. In addition, a noise reduction scheme is introduced and combined with the estimator. In implementation, the DCT-based estimator has the advantages of utilizing mature fast DCT algorithms and compatible FFT algorithms, which is favorable to other matrix-based channel estimation methods.
Reduction of Doppler-induced ICI by interference prediction
(2004)
Yeh, YH
;
Chen, SG
;
交大名義發表
;
National Chiao Tung University
Although wireless OFDM systems are robust against frequency-selective fading and ISI effect, their relatively long symbol lengths are vulnerable to time-selective fading and ICI effect in mobile environments due to Doppler spread. However, commonly a time-selective fading channel is linearly time-varying from symbol to symbol, for the existing wireless communication systems and vehicle speed limits. The linear property greatly reduces channel parameters. Based on this condition, we propose an ICI-reduction method. The ICI-reduction method first solves the linear channel parameters of each path, and then combines with a decision-feedback method to predict the ICI values from the estimated channel information, followed by the subtraction of the ICI components. Further, the proposed algorithm adopts an iterative ICI refinement technique to enhance the ICI prediction accuracy. The simulation results show that the new method can effectively reduce the ICI and error floor of symbol error rate. The proposed algorithm is further simplified. The simplified version still maintains almost the same performance as before, with a much reduced complexity.
Scalable VLSI architectures for full-search block matching algorithms
(1996)
Yeh, YH
;
Lee, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics