Browsing by Author "Yen, Cheng-Cheng"

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Failure of on-chip power-fall ESD clamp circuits during system-level ESD test
(2007)
Yen, Cheng-Cheng
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
Four different on-chip power-rail electrostatic discharge (ESD) protection circuits, (1) with typical RC-triggered; (2) with NMOS+PMOS feedback; (3) with PMOS feedback; and (4) with cascaded PMOS feedback, have been designed and fabricated in a 0.18-mu m CMOS technology to investigate their susceptibility to system-level ESD test. During the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuit provides the lock function to keep the main ESD device in a "latch-on" state. The latch-on ESD device, which is often designed with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. From the experimental results, two kinds of on-chip power-rail ESD clamp circuits with feedback structures are highly sensitive to transient-induced latchup-like failure than others.
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
(2008-11-01)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
On-chip power-rail electrostatic discharge (ESD) protection circuit designed with active ESD detection function is the key role to significantly improve ESD robustness of CMOS integrated circuits (ICs). Four power-rail ESD clamp circuits with different ESD-transient detection circuits were fabricated in a 0.18-mu m CMOS process and tested to compare their system-level ESD susceptibility, which are named as power-rail ESD clamp circuits with typical RC-based detection, PMOS feedback, NMOS+PMOS feedback, and cascaded PMOS feedback in this work. During the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuits provides the lock function to keep the ESD-clamping NMOS in a "latch-on" state. The latch-on ESD-clamping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. A modified power-rail ESD clamp circuit is proposed to solve this problem. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robustness, and without suffering the latchup-like failure during the system-level ESD test.
Latchup-like failure of power-rail ESD clamp circuits in CMOS integrated circuits under system-level ESD test
(2007)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
電機學院
;
College of Electrical and Computer Engineering
Two different on-chip power-rail electrostatic discharge (EaD) protection circuits, (1) with NMOS and PMOS feedback, and (2) with cascaded PMOS feedback have been designed and fabricated in a 0.18-mu m CMOS technology to investigate their susceptibility to system-level ESD test. The main purpose for adopting the feedback loop into the power-rail ESD clamp circuits is to avoid the false triggering during a fast power-up operation. However, during the system-level ESD test, where the ICs in a microelectronics system have been powered up, the feedback loop used in the power-rail ESD clamp circuit provides the lock function to keep the main ESD device in a "latch-on" state. The latch-on ESD device, which is often designed with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. The susceptibility of power-rail ESD clamp circuits with the additional board-level noise filter to the system-level ESD test is also investigated. To meet high system-level ESD specifications, the chip-level ESD protection design should be considered with the transient noise during system-level ESD stress.
New 4-Bit Transient-to-Digital Converter for System-Level ESD Protection in Display Panels
(2012-02-01)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
電機學院
;
College of Electrical and Computer Engineering
A new on-chip 4-bit transient-to-digital converter for system-level electrostatic discharge (ESD) protection design is proposed. The proposed converter is designed to detect ESD-induced transient disturbances and transfer different ESD voltages into digital codes under system-level ESD tests. The experimental results in a 0.13-mu m CMOS integrated circuit with 1.8-V devices have confirmed the detection function and digital output codes. The proposed on-chip transient-to-digital converter can be code-signed with firmware operations to effectively enhance immunity of display systems against system-level ESD stresses.
New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance
(2010-10-01)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18-mu m complementary-metal-oxide-semiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.
New transient detection circuit for system-level ESD protection
(2008)
Yen, Cheng-Cheng
;
Liao, Chi-Sheng
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit can be co-designed to fix the system-level ESD issues. The circuit performance to detect different positive and negative ESD-induced fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.18-mu m CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping.
On-chip detection circuit for protection design in display panel against electrical fast transient (EFT) disturbance
(2011)
Yen, Cheng-Cheng
;
Ker, Ming-Dou
;
Lin, Wan-Yen
;
Yang, Che-Ming
;
Chen, Shih-Fan
A new on-chip detection circuit is proposed for electrical fast transient (EFT) protection design in a display system. For microelectronic products, electrical transient disturbances often cause upset or frozen states under the IEC test standard. The output signal of the proposed detection circuit can be used as a firmware index to execute system automatic recovery operations and to release the EFT-induced locked states in display panels. The circuit function to detect positive or negative electrical transients has been investigated in HSPICE simulation and verified in silicon chip. The experimental results have confirmed successful circuit performance under EFT tests. With hardware/firmware co-design, the immunity of a display system against electrical transient disturbance has been significantly improved.
On-chip transient detection circuit for system-level ESD protection in CMOS ICs
(2006)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
Shih, Pi-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed in this paper. The circuit performance to detect different positive and negative fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.13-mu m CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping. The proposed transient detection circuit can be further cooperated with power-on reset circuit to improve the immunity of CMOS IC products against system-level ESD stress.
On-chip transient detection circuit for system-level ESD protection in CMOS integrated circuits to meet electromagnetic compatibility regulation
(2008-02-01)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
Shih, Pi-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. The circuit performance to detect different positive and negative fast electrical transients has been investigated by the HSPICE simulator and verified in a silicon chip. The experimental results in a 0.13-mu m CMOS integrated circuit (IC) have confirmed that the proposed on-chip transient detection circuit can be used to detect fast electrical transients during the system-level ESD events. The proposed transient detection circuit can be further combined with the power-on reset circuit to improve the immunity of the CMOS IC products against system-level ESD stress.
POWER-RAIL ESD PROTECTION CIRCUIT WITHOUT LOCK-ON FAILURE
(2009-04-02)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
Chen, Tung-Yang
An ESD protection circuit including a discharge device, a first detection circuit, and a second detection circuit. The discharge device provides a discharge path between a first power rail and a second power rail when the discharge device is activated. The discharge device stops providing the discharge path when the discharge device is de-activated. The first detection circuit is coupled between the first and the second power rails. The first detection circuit activates the discharge device when an ESD event occurs in the first power rail. The second detection circuit de-activates the discharge device when the ESD event does not occur in the first power rail.
Protection Design Against System-Level ESD Transient Disturbance on Display Panels
(2010-01-01)
Ker, Ming-Dou
;
Lin, Wan-Yen
;
Yen, Cheng-Cheng
;
Yang, Che-Ming
;
Chen, Tung-Yang
A hardware/firmware system co-design has been proposed in this work to protect display electronic products against system-level electrostatic discharge (ESD) transient disturbance. By including transient detection circuit, the firmware can execute system recovery procedure to recover all electrical functions under system-level ESD tests. The transient detection circuit is designed to detect different positive and negative fast electrical transients and verified in a 0.13 mu m CMOS process. The experimental results have confirmed that the proposed hardware/firmware design can successfully improve the susceptibility of display products against system level ESD zapping.
SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance
(2014-01-01)
Ker, Ming-Dou
;
Lin, Wan-Yen
;
Yen, Cheng-Cheng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new silicon controlled rectifier (SCR)-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance is proposed. The circuit function to detect positive or negative electrical transients during system-level electrostatic discharge (ESD) and electrical fast transient (EFT) tests has been verified in silicon chip. The experimental results in a 0.18-mu m CMOS process have confirmed that the new proposed detection circuit can successfully memorize the occurrence of system-level electrical transient disturbance events. The detection results can be cooperated with firmware design to execute system recovery procedures, therefore the immunity of microelectronic systems against system-level ESD or EFT tests can be effectively improved. (C) 2013 Elsevier Ltd. All rights reserved.
System-level ESD protection design with on-chip transient detection circuit
(2006)
Yen, Cheng-Cheng
;
Ker, Ming-Dou
;
Shih, Pi-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new on-chip transient detection circuit for system-level electrostatic (d) under bar ischarge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit has been analyzed to fix the system-level ESD issues. The circuit performance to detect different positive and negative fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.13-mu m CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping.
The Effect of IEC-Like Fast Transients on RC-Triggered ESD Power Clamps
(2009-06-01)
Yen, Cheng-Cheng
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
Four power-rail electrostatic-discharge (ESD) clamp circuits with different ESD-transient detection circuits have been fabricated in a 0.18-mu m CMOS process to investigate their susceptibility against electrical fast-transient (EFT) tests. Under EFT tests, where the integrated circuits in a microelectronic system have been powered up, the feedback loop used in the power-rail ESD clamp circuits may lock the ESD-clamping NMOS in a "latch-on" state. Such a latch-on ESD-clamping NMOS will conduct a huge current between the power lines to perform a latchuplike failure after EFT tests. A modified power-rail ESD clamp circuit has been proposed to solve this latchuplike failure and to provide a high-enough chip-level ESD robustness.
TRANSIENT DETECTION CIRCUIT
(2009-10-29)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
Liao, Chi-Sheng
;
Chen, Tung-Yang
A transient detection circuit coupled between a first power line and a second power line and including a first control unit, a setting unit, and a voltage regulation unit. The first control unit generates a first control signal. The first control signal is at a first level when an electrostatic discharge (ESD) event occurs. The first control signal is at a second level when the ESD event does not occur. The setting unit sets a first node. The first node is set at the second level when the first control signal is at the first level. The voltage regulation unit regulates the first node. The voltage regulation unit regulates the level of the first node at the second level when the first control signal is at the second level.
TRANSIENT DETECTION CIRCUIT FOR ESD PROTECTION
(2009-07-23)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
Liao, Chi-Sheng
;
Chen, Tung-Yang
A transient detection circuit including a detecting unit, a setting unit, and a memory unit. The transient detection circuit provides an information signal to an external instrument when an electrostatic discharge (ESD) event occurs. The detecting unit is coupled between a first power line and a second power line for detecting the ESD event. The setting unit sets a level of a first node according to the detection result. The memory unit controls the information signal according to the level of the first node. The information signal is at a first level when the ESD event occurs in the first power line.
Transient Detection Circuit for System-Level ESD Protection and Its On-Board Behavior with EMI/EMC Filters
(2008)
Ker, Ming-Dou
;
Liao, Chi-Sheng
;
Yen, Cheng-Cheng
;
電機學院
;
College of Electrical and Computer Engineering
A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. The circuit performance of detecting fast electrical transients has been verified in a 0.18-mu m CMOS integrated circuit (IC). The experimental results have confirmed that the proposed on-chip transient detection circuit can detect positive and negative fast electrical transients during system-level ESD zapping. Three board-level noise filtering networks have been investigated their enhancement on detection range of the proposed on-chip transient detection circuit. The chip-level solution can be further co-designed with the board-level solution in order to meet high system-level ESD specification.
TRANSIENT TO DIGITAL CONVERTERS
(2009-09-17)
Ker, Ming-Dou
;
Yen, Cheng-Cheng
;
Liao, Chi-Sheng
;
Chen, Tung-Yang
A digital converter including a first adjustment unit and a first transient detection unit. The first adjustment unit adjusts amplitude of an electrostatic discharge (ESD) pulse to generate a first adjustment signal when an ESD event occurs in a first power line and a second power line is at a complementary level. The first transient detection unit generates a first digital code according to the first adjustment signal.
Transient-Induced Latchup in CMOS ICs Under Electrical Fast-Transient Test
(2009-06-01)
Yen, Cheng-Cheng
;
Ker, Ming-Dou
;
Chen, Tung-Yang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The occurrence of transient-induced latchup (TLU) in CMOS integrated circuits (10) under electrical fast-transient (EFT) tests is studied. The test chip with the parasitic silicon-controlled-rectifier (SCR) structure fabricated by a 0.18-mu m CMOS process was used in EFT tests. For physical mechanism characterization, the specific "swept-back" current caused by the minority carriers stored within the parasitic PNPN structure of CMOS ICs is the major cause of TLU under EFT tests. Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against TLU under EFT tests. By choosing the proper components in each noise filter network, the TLU immunity of CMOS ICs against EFT tests can be greatly improved.
Transient-induced latchup in CMOS integrated circuits due to electrical fast transient (EFT) test
(2007)
Yen, Cheng-Cheng
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
The transient-induced latchup (TLU) in CMOS ICs under electrical fast transient (EFT) test has been investigated by experimental verification. With positive and negative voltage pulses under EFT test, the TLU can be triggered on in CMOS ICs with the parasitic pnpn structure. The physical mechanism of TLU in CMOS ICs has been developed with experimental verification in time domain. All the experimental evaluations have been verified with the silicon-controlled rectifier (SCR) test structure fabricated in a 0.18-mu m CMOS technology.